>-----Original Message----- >From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] >On Behalf Of Gilles Chanteperdrix >Sent: jeudi 25 octobre 2007 19:48 >To: Patrick >Cc: [email protected] >Subject: Re: [Xenomai-help] Event flag from ISR > >Patrick wrote: > > Hi all, > > > > > > > > I am using a RT event flag structure to start a task from an ISR. > > > > The task waits on rt_event_wait and when the IRQ occurs the ISR >executes > > rt_event_signal (the ISR code only clears the flag and calls > > rt_event_signal). > > > > I'm using an oscilloscope to measure the length of the ISR and the >first > > occurrence lasts about 20us and all the next occurrences last about >4us. > > > > > > > > My question is why the first ISR is so long? > > > > > > > > For information I use xenomai 2.4 rc4 on ARM pxa270 machine with >2.6.20 > > kernel. > >Typical worst case interrupt latency on ARM is around 50 us, so 20 us is >not that long. What you are observing is probably a cache effect. In >this case, you should observe 20us after each user-space context switch >since on ARM, cache is flushed at each user-space context switch.
It could make sense to have a look at the L4-embedded microkernel which uses the Fast Context Switch Extension (FCSE) of ARM and to adapt the mm switch accordingly. But as far as I remember, this could introduce some limitations to a process size since all threads are sharing a same virtual address space subdivided into smaller virtual regions. Benchmarks with FCSE reported some significant improvements and I know this technics is commonly used for virtualization layer on ARM. > >-- > > > Gilles Chanteperdrix. > >_______________________________________________ >Xenomai-help mailing list >[email protected] >https://mail.gna.org/listinfo/xenomai-help Daniel _______________________________________________ Xenomai-help mailing list [email protected] https://mail.gna.org/listinfo/xenomai-help
