Gabriele Moabiti wrote:
Please do not drop the list from the CC.
> The asm x86 code is a "legacy" code developed in x86 plain binary asm
> (written with tasm and can't be re-written of course)
I do not understant the "of course". If this is assembly, then run a
disassembler and you will get the source.
> with fixed addresses for data and code (I'll call SIS in the follow).
> When one of the follow exception occurred
>
> * 0x00 Divide by zero
> * 0x01 Debug exception
> * 0x03 Int3
> * 0x04 Overflow
> * 0x05 Array bounds check
> * 0x06 Illegal Opcode
> * 0x07 FPU not available
> * 0x08 Double fault
> * 0x09 Coprocessor segment overrun
> * 0x0a Invalid task state
> * 0x0b Segment not present
> * 0x0c Stack exception
> * 0x0d General Protection Fault
> * 0x0e Page fault
> * 0x0f Reserved
> * 0x10 Coprocessor error
>
> SIS expects some custom actions (set internal flags, save errors and so on).
>
> I have mapped SIS in a kernel module and mapped to user space with xenomai.
> Now I though to execute SIS in ring 3 (as rt task) and trap the exceptions at
> ring 0 (always inside real time constraints).
>
> The result should be
>
> <C code>
> <set custom exceptions>
> <SIS code>
> <set default exceptions>
> <C code>
>
> In the "C code" part I'll use rtnet.
I think you are traping yourself with impossible constraints.
Anyway, the only way is register a custom exception handler using rthal
functions. In your trap handler, you may wake up a user-space server
thread which role is to handle exceptions (in user-space). This means that:
- upon exception, you have a switch to the user-space server thread
context, this will be slow;
- you have to rewrite the exception handling code, you can not rely
on the exception handling code that was written in the assembly blob.
I do not think it is a good idea to simply override the exception
vectors, the kernel uses them, and you certainly want the kernel to
continue working.
--
Gilles.
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