On Fri, Mar 04, 2011 at 08:51:00AM +0100, Philippe Gerum wrote:
> I'm not saying this would be impossible to enable MSIs there, I'm just
> saying that so far: nobody cared. Terrae incognitae.
Philippe,
I read adeos-ipipe-2.6.36-powerpc-2.12-02.patch in order to
re-acquaint myself with adeos. While I do not pretend to really
understand it, I did notice an incongruity in the interrupt handling
for my particular board.
The function, fsl_msi_cascade, in arch/powerpc/sysdev/fsl_msi.c:185
has in the non-ipipe version two different actions
desc->chip->unmask(irq);
desc->chip->eoi(irq);
depending on whether the controller is an ipic or mpic. The ipipe
code unconditionally executes ipic/unmask.
I noticed that the function
cpm_cascade() in arch/powerpc/platforms/8xx/m8xx_setup.c
does call eoi(), so I guessed that the eoi() in fsl_msi_cascade()
might have been overlooked. Putting the eoi() into the ipipe version
lets the machine handle the interrupts, and my test programs will even
run with the PCIe card and driver.
However, I am really making a grab in the dark, and I see strange
warnings like unexpected (in_irq() || irqs_disabled()) from
kernel/softirq.c:143 and so on.
Also, more interrupts appear for my card in /proc/interrupts than
expected.
Is this any kind of hint, or am I just completely lost?
Thanks,
Richard
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