> -----Ursprüngliche Nachricht----- > Von: Gilles Chanteperdrix [mailto:[email protected]] > Gesendet: Donnerstag, 11. Juni 2015 19:35 > An: Lopes, Alexandre > Cc: Gilles Chanteperdrix; Lowell Gilbert; [email protected] > Betreff: Re: AW: [Xenomai] init failed code -19 on Cyclone V SoC > > The Linux mainline code refuses to start the global timer with old > revisions of the cortex A9 core which global timer is not exactly the same > as with newer revisions (there is a difference in what condition triggers > the timer interrupt which make it possible for the old revisions timer to > not receive an interrupt if the programmed delay is too short, whereas it > can not happen with newer versions). So, the SOCs in mainline based on > such old versions do not even bother to declare the global timer registers > in the DT. >
I see. I've noticed the DTS for the Zynq-7000 does have a node for the global timer. Since I believe the Cyclone V and the Zynq-7000 use identical Cortex A9 revisions, the reason might then be that Altera never pushed for it (supported by the fact that they don't use it even in their vendor-specific Kernel, like I replied to Lowell) > The I-pipe clock source does not care about the timer, it only needs the > free running counter, and actually has been using it long before the arm > global timer driver was merged. This free running counter works fine in > both cases (and has an unparalleled resolution and latency, which makes it > interesting for emulating a tsc), so, I have patched up the global timer > code to keep the clocksource even with old revisions and only skip the > clockevent device registration, so that we can add the global timer > register declarations in DT and have the clocksource without the timer. > But this is a hack, really, it means that we have to add the DT data in > the I-pipe patch, and this is going to byte us when mainline decides to > restructure the global timer support. Right, adding the DTS nodes in the I-pipe patch sounds far from ideal. In any case, since that's how it's being done atm, here's a patch which should work on any of the Altera's Cortex A9 based SoCs (Cyclone and Arria): ================================================================== From fe7c1fff5a404daa284f2fc0253c44c689beeb54 Mon Sep 17 00:00:00 2001 From: Alexandre Lopes <[email protected]> Date: Fri, 12 Jun 2015 15:02:53 +0200 Subject: [PATCH] DT Cortex A9 global timer for Altera SoCs --- arch/arm/boot/dts/socfpga.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4472fd9..2507455 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -647,6 +647,15 @@ clocks = <&mpu_periph_clk>; }; + /* Global timer */ + timer@fffec200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffec200 0x20>; + interrupts = <1 11 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; -- 1.7.9.5 ================================================================== Alexandre _______________________________________________ Xenomai mailing list [email protected] http://xenomai.org/mailman/listinfo/xenomai
