Hi, I sent this to dri-devel, but i want to send it here as well to get
wider testing if possible...
Here is a patch that adds the ability to control the core and memory
clocks on a Banshee/V3 (only tested on V3 3500). It works for me, and
allows me to underclock my V3 3500 to 166Mhz (instead of 183). I would
like people to experiment and test... some frequencies work for me (like
166) but others don't (147Mhz, for example). I believe that this is due
to "quirks" in the algorithm to set the PLL, or in hardware quirks on the
card.
This patch could damage your card if you're not careful. only the brave
should try.
This patch adds two new config file options: GFXClock <int> and
MemClock<int>. (yes, i could have made them frequencies instead, but i
chose not to...simplifies code). MemClock only has meaning on a Banshee
that has separate core and mem controls, a V3 does not. So to set the
core of my V3 to 166Mhz, i added the line
Option "GFXClock" "166"
to the driver section. I would like people to try this if they dare, and
report back to me any successes/failures they may have (specifically,
which speeds work and which ones don't on what hardware) I'd also like
to hear from people with V4/5 specs to see what needs to be changed to
support those card, as well as older Voodoo/2 chipsets.. Banshee support
is included, but not tested.
I'll also come out with a simple utility to change the clock/mem speed on
the fly, when i get the time....
note: you can use this code to overclock your hardware, but i would
definately suggest otherwise... the whole purpose i had in writing this
patch was so i could -underclock- my overly hot V3 3500 in a small,
underventilated case. Don't come crying to me or anyone else if you
overclock your hardware and it stops working.
enjoy..
john.c
--
John Clemens http://www.deater.net/john
[EMAIL PROTECTED] ICQ: 7175925, IM: PianoManO8
"I Hate Quotes" -- Samuel L. Clemens
Index: tdfx_driver.c
===================================================================
RCS file: /cvs/xc/programs/Xserver/hw/xfree86/drivers/tdfx/tdfx_driver.c,v
retrieving revision 1.91
diff -r1.91 tdfx_driver.c
140a141,145
> /* For changing the default clock speeds */
> static int PLLtoFreq(int pll);
> static Bool SetGfxPLL(ScrnInfoPtr pScrn, int freq);
> static Bool SetMemPLL(ScrnInfoPtr pScrn, int freq);
>
166a172
> /* yes. --jc */
176c182,184
< OPTION_DRI
---
> OPTION_DRI,
> OPTION_GFX_CLOCK,
> OPTION_MEM_CLOCK
187a196,197
> { OPTION_GFX_CLOCK, "GFXClock", OPTV_INTEGER, {0}, FALSE },
> { OPTION_MEM_CLOCK, "MemClock", OPTV_INTEGER, {0}, FALSE },
675a686
> int gfxclk, memclk;
1031a1043,1051
>
> if (xf86GetOptValInteger(pTDFX->Options, OPTION_GFX_CLOCK, &gfxclk)) {
> if (gfxclk != 0)
> SetGfxPLL(pScrn, gfxclk);
> }
> if (xf86GetOptValInteger(pTDFX->Options, OPTION_MEM_CLOCK, &memclk)) {
> if (memclk != 0)
> SetMemPLL(pScrn, memclk);
> }
1097d1116
<
1361a1381,1392
> /* Converts a PLL register value to a frequency (Khz) [EMAIL PROTECTED] */
> static int
> PLLtoFreq(int pll) {
> int freq;
> int N = ((pll & 0x0000FF00) >> 8);
> int M = ((pll & 0x000000FC) >> 2);
> int K = (pll & 0x00000003);
>
> freq = (int)((REFFREQ * (N+2))/((M+2)*(1 << K)));
> return freq;
> }
>
1437c1468,1472
< #if 0
---
> /*
> * Sets pllCtrl2 register PLL to the desired memory frequency.
> * Works on Banshee, Not V3 (V5?), according to specs I have.
> * pllCtrl2 is a completely different beast on V3. [EMAIL PROTECTED]
> */
1439c1474
< SetupMemPLL(int freq) {
---
> SetMemPLL(ScrnInfoPtr pScrn, int freq) {
1441d1475
< vgaTDFXPtr tdfxReg;
1442a1477,1501
> int mempll;
>
> /* Convert passed in freq (Mhz) to Khz. */
> freq = freq*1000;
>
> TDFXTRACE("SetMemPLL start\n");
> pTDFX=TDFXPTR(pScrn);
>
> if (pTDFX->ChipType == PCI_CHIP_BANSHEE) {
> mempll=pTDFX->readLong(pTDFX, PLLCTRL2);
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Original Mem Clock : %dKhz\n",
> PLLtoFreq(mempll));
> if (freq > PLLtoFreq(mempll))
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
> " **** Warning! Overclocking Memory **** \n");
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Setting Mem Clock to %dKhz\n",freq);
>
> mempll=CalcPLL(freq, &f_out, 1);
> pTDFX->writeLong(pTDFX, PLLCTRL2, mempll);
>
> } else {
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
> "Can't independently set Memory Clock, not a Banshee\n");
> return FALSE;
> }
1444,1450d1502
< TDFXTRACE("SetupMemPLL start\n");
< pTDFX=TDFXPTR();
< tdfxReg=(vgaTDFXPtr)vgaNewVideoState;
< tdfxReg->mempll=CalcPLL(freq, &f_out);
< pTDFX->writeLong(pTDFX, PLLCTRL1, tdfxReg->mempll);
< TDFXTRACEREG("Mem PLL freq=%d f_out=%d reg=%x\n", freq, f_out,
< tdfxReg->mempll);
1453a1506,1510
> /*
> * Sets pllCtrl1 register PLL to the desired Core Speed (Banshee)
> * or Core/Mem speed (V3(/V5?)). I guess the mem and core clocks
> * on V3 are synchronous. [EMAIL PROTECTED]
> */
1455c1512
< SetupGfxPLL(int freq) {
---
> SetGfxPLL(ScrnInfoPtr pScrn, int freq) {
1457d1513
< vgaTDFXPtr tdfxReg;
1458a1515
> int gfxpll;
1460,1469c1517,1534
< TDFXTRACE("SetupGfxPLL start\n");
< pTDFX=TDFXPTR();
< tdfxReg=(vgaTDFXPtr)vgaNewVideoState;
< if (pTDFX->chipType==PCI_CHIP_BANSHEE)
< tdfxReg->gfxpll=CalcPLL(freq, &f_out, 1);
< else
< tdfxReg->gfxpll=CalcPLL(freq, &f_out, 0);
< pTDFX->writeLong(pTDFX, PLLCTRL2, tdfxReg->gfxpll);
< TDFXTRACEREG("Gfx PLL freq=%d f_out=%d reg=%x\n", freq, f_out,
< tdfxReg->gfxpll);
---
> /* Convert passed in freq (Mhz) to Khz */
> freq = freq*1000;
>
> TDFXTRACE("SetGfxPLL start\n");
> pTDFX=TDFXPTR(pScrn);
>
> gfxpll = pTDFX->readLong(pTDFX, PLLCTRL1);
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Original Core Clock : %dKhz\n",
> PLLtoFreq(gfxpll));
> if (freq > PLLtoFreq(gfxpll))
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
> " **** Warning! Overclocking Core%s! ****\n",
> (pTDFX->ChipType == PCI_CHIP_VOODOO3)?"/Mem":"");
> xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Setting Core Clock to %dKhz\n", freq);
>
> gfxpll=CalcPLL(freq, &f_out, (pTDFX->ChipType==PCI_CHIP_BANSHEE));
> pTDFX->writeLong(pTDFX, PLLCTRL1, gfxpll);
>
1472d1536
< #endif
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