You might try asking Garret D'Amore, since I don't think he watches this list.
(Though he's limited in what he can say about his former employer's systems,
they are letting him integrate a bunch of code for them into OpenSolaris, so
it may be in the areas they're willing to be public.)
-Alan Coopersmith- alan.coopersmith at sun.com
Sun Microsystems, Inc. - X Window System Engineering
Martin Bochnig wrote:
>> It will probably fail during pci scanning. Anyways as long as TADPOLE have
>> made the same design decision on the SPARCbook 6500
>
> Aehm, I forgot the "what and why": To limit the max number of pci bus'es per
> domain to 256, instead of the UltraSPARC default setting of 4096.
> The SIGBUS occurrs when misc functions in Pci.c and sparcPci.c try to access
> bus 257.
> Simply changing that number by hardwiring it in Pci.h to 256 is not only a
> bad idea (as it affects most non-TADPOLE systems, but it doesn't even work
> at all for some reason (strange SIGBUS much earlier instantly after the pci
> bridge would have been identified by sparcPci.c).
> My current "fix" doesn't deserve that name: The m64 device happens to be the
> 13th pci chip identified by sparcPci.c on the 500SX. So I just set the max
> number of pci devices to 13 in Pci.h .
> And it works, because nobody tries to access bus 257 that way, but I need
> some criteria, some logic, how to solve this properly. Automatically and
> without any consequences for any other platforms.
>
> ~m
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