2009/10/28 Linus Torvalds <torva...@linux-foundation.org>:
>
>
> On Sun, 25 Oct 2009, Gábor Stefanik wrote:
>>
>> Also, is there any reference to a failed channel switch in the log?
>
> I've been debugging this some more, and it looks like there are more
> issues at play than just the DMA problem.
>
> With the b43 driver enabled, I seem to be unable to reliably suspend and
> resume. Sometimes the machine just locks up hard, but sometimes I get
> something like this on the resume path:
>
>        b43-phy0 debug: Resuming...
>        b43-phy0 debug: Device resumed.
>        ...
>        b43-phy0: Loading firmware version 478.104 (2008-07-01 00:50:23)
>        b43-phy0 debug: b2062: Using crystal tab entry 19200 kHz.
>        b43-phy0 debug: RC calib: Failed to switch to channel 7, error = -5
>        b43-phy0 debug: Chip initialized
>        b43-phy0 debug: PIO initialized
>        b43-phy0 debug: QoS disabled
>        b43-phy0 debug: Wireless interface started
>        b43-phy0 debug: Adding Interface type 2
>
> and when that happens, it appears that then the _next_ suspend/resume
> cycle will fail with a hard lockup. And sometimes the hard lockup happens
> on the very first resume.
>
> But maybe that "Failed to switch to channel 7" error is entirely unrelated
> to the "Locks up hard on resume" problem. But the lock-up seems to be tied
> to the b43 driver too - the machine seems stable if I don't load that
> module at all.
>
> What seems a bit odd is how the b43_lpphy_op_init() seems to try to switch
> to channel 7 _twice_. It does:
>
>        ...
>        lpphy_radio_init(dev);
>        lpphy_calibrate_rc(dev);
>        err = b43_lpphy_op_switch_channel(dev, 7);
>        ...
>
> and that lpphy_calibrate_rc() call will already have done the channel
> switch for the lpphy_rev0_1_rc_calib() case. Maybe it should just switch
> to channel 7 unconditionally before doing the lpphy_calibrate_rc()?

What we do is exactly what the spec calls for - specifically, rev.2+
cards don't switch to channel 7 during RC calibration, while rev.0/1
SoCs can have an NVRAM variable specifying a predetermined RC-Cap
value, in which case the actual RC calibration doesn't even run
(though the latter is not yet implemented). However, just switching to
channel 7 at the beginning looks saner - Larry, what do you think
about it?

>
> I dunno. I don't know the code, I don't know the hardware, the above is
> just a random musing based on looking at the code around that warning
> case.
>
>                                Linus
>



-- 
Vista: [V]iruses, [I]ntruders, [S]pyware, [T]rojans and [A]dware. :-)
_______________________________________________
Bcm43xx-dev mailing list
Bcm43xx-dev@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/bcm43xx-dev

Reply via email to