Hi Chenwei, What version of the Xilinx tools are you using? I think this is easy to fix, but I'm surprised I didn't see this error when I compiled my test models.
Cheers, Jack On Fri, 5 Jun 2015 at 12:02 Chenwei Cai <caichenwei1...@gmail.com> wrote: > Thanks Jack, > > The qdr_transpose seems to work appropriately now. And I am now using the > qdr_transpose block to construct my model which will be executed with ROACH > II, as you can check out in the following url: > https://www.dropbox.com/s/1wcz0lhmjgcuwua/Screenshot%20from%202015-06-05%2015%3A35%3A44.png?dl=0. > The library I am using is the one Jack merged last week ( > http://www.mail-archive.com/casper@lists.berkeley.edu/msg05947.html). > > The compile goes smoothly, only to find an error at the last of compile. > See the log below, which records the last part of compile. > > Running DRC. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<81>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<83>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<113>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<61>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<63>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<17>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/fifo_din_buf1<31>> is incomplete. The signal does not drive any load > pins > in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_RAMA_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_RAMB_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_RAMC_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_RAMB_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_RAMC_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_RAMC_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_RAMA_D1_DPO> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_RAMD_D1_O> is incomplete. > The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:367 - The signal > > <fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 > g/FIFO/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_D1_O> is incomplete. The > signal does not drive any load pins in the design. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<10 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<11 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<12 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<20 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<13 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<21 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<14 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<22 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<30 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<15 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<23 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<31 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<16 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<24 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<32 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<17 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<25 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<33 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<18 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<26 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<34 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<19 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<27 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<35 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<28 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<29 > >>:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<0> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<1> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<2> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<3> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<4> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<5> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<6> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<7> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<8> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > WARNING:PhysDesignRules:1441 - Issue with pin connections and/or > configuration > on > > block:<qdr0_controller/qdr0_controller/qdrc_infrastructure_inst/IDDR_qdr_q<9> > >:<ILOGICE1_IFF>. The IFFTYPE is DDR and the Q2 output pin of IFF is > not > used. > ERROR:PhysDesignRules:1763 - Issue with pin connections and/or > configuration on > > block:<qdr1_controller/qdr1_controller/qdrc_infrastructure_inst/IODELAY_sa<20 > >>:<IODELAYE1_IODELAYE1>. For DELAY_SRC IO or O programming the ODATAIN > input pins of IODELAYE1 must be connected. > ERROR:Bitgen:25 - DRC detected 1 errors and 63 warnings. Please see the > previously displayed individual error or warning messages for more > details. > =================================================================== > Flow run time summary: (00:27:41 seconds total) > System update............00:00:00 > Design Rules Check.......00:00:00 > Xilinx System Generator..00:10:08 > Base system copy.........00:00:00 > IP creation..............00:00:00 > EDK files creation.......00:00:06 > IP elaboration...........00:00:00 > Software creation........00:00:00 > EDK/ISE backend..........00:17:26 > =================================================================== > > > After the compile, the .bof.gz, .fpg, and .info files appear in the > bit_file folder, but I fail to find the .bof file in that folder! Somebody > encountered such a problem before or has some ideas about that? > > Thanks! > > > > On Mon, Apr 27, 2015 at 4:06 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Chenwei, >> >> A couple of general comments -- >> 1. strictly speaking you should have xilinx "gateway out" blocks between >> the slice blocks and the scope, since the scope needs simulink (not xilinx) >> data types as input. Having said that, it'll probably work the way you have >> the design set up, it might issue warnings though. >> 2. Block sizes of 2^2 probably work, but I'd recommend testing with >> something a little bigger in case there are some special cases which stop >> the small block size from behaving as expected. >> >> Now to explain (hopefully!) your results -- >> >> The qdr transpose is really a reorder, that is, no rearrangement of the >> bits within the 36- bit words you're writing will ever take place. Thus, if >> the bottom 18 bits going in are always 2, the bottom bits of the output >> will also always be 2. >> >> It is a transpose in the sense that as each word comes in, it is written >> row by row in to a matrix with in_block_size columns, and out_block_size >> rows. It is then reordered such that it is read out column by column. >> >> Some hastily written python code showing how the output is related to the >> input (which may or may not be helpful): >> >> import pylab >> >> in_block_size = 2**3 >> out_block_size = 2**4 >> n_cycles = 4 #cycles to plot >> in_vec = range(in_block_size) * out_block_size * n_cycles >> out_vec = [0 for i in range(len(in_vec))] >> print 'in', in_vec >> for i in range(n_cycles): >> offset = i*in_block_size*out_block_size >> for col in range(in_block_size): >> for row in range(out_block_size): >> out_vec[offset + row + col*out_block_size] = in_vec[offset + col + >> row*in_block_size] >> >> print 'out:', out_vec >> pylab.subplot(2,1,1) >> pylab.title('in') >> pylab.plot(in_vec) >> pylab.subplot(2,1,2) >> pylab.title('out') >> pylab.plot(out_vec) >> pylab.show() >> >> I'm not sure I can entirely explain the output you get. (Ignoring the '2' >> in your LSBs, the block input is [0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, ...] >> For an input and output block size of 4, [i think] the output should be: >> [0, 4, 0, 4, 1, 5, 1, 5, 2, 6, 2, 6, 3, 7, 3, 7, <repeat>]. >> It doesn't seem to be quite that so I would suggest that either blocks >> that small don't work or (perhaps more likely) something is up with your >> sync-ing. If you look inside the block, you'll see a reorder, with text >> saying 'order=3' or something like that (it is dependent on the qdr >> transpose parameters you've chosen. Note, if you change the 'double buffer' >> parameter of that block to 1, it will always have an order of 2, which can >> be useful). Your sync period needs to be a multiple of both the matrix size >> (in your case, 4*4 = 16 cycles) and also the number of reorder orders. Eg, >> a multiple of 16*3 = 48 cycles. (see >> https://casper.berkeley.edu/memos/sync_memo_v1.pdf for more info on sync >> pulses and their pitfalls). I would suggest, for testing, that you input >> only a single sync into the block, at least until you are familiar with >> it's working. >> >> Cheers, (and hope that helps!) >> Jack >> >> >> >> On Fri, 24 Apr 2015 at 15:19 Chenwei Cai <caichenwei1...@gmail.com> >> wrote: >> >>> Thanks Jack and Dan. >>> >>> Regarding the qdr_transpose block, I am still confused. I have set up >>> some simple models to figure out how this block works, but they just lead >>> me to a greater confusion. >>> >>> One of the models is like this: >>> https://www.dropbox.com/s/dwhukesqqhdgllf/Screenshot%20from%202015-04-24%2018%3A26%3A33.png?dl=0 >>> . >>> The parameters of the counter are >>> https://www.dropbox.com/s/hboym3amfbrcom9/Screenshot%20from%202015-04-24%2018%3A26%3A51.png?dl=0 >>> . >>> And the parameters of the qdr_transpose block are >>> https://www.dropbox.com/s/o9ke9wpur5bucwt/Screenshot%20from%202015-04-24%2018%3A27%3A20.png?dl=0 >>> . >>> >>> What I expect to do is to transpose the matrix like this >>> https://www.dropbox.com/s/cogwtc3sk0cnuem/Screenshot%20from%202015-04-24%2019%3A09%3A27.png?dl=0. >>> I have no idea whether the model is doing the same thing as I expect it to >>> finish, since the execution of the simulation results in this >>> https://www.dropbox.com/s/c28ya7koy5nyisi/Screenshot%20from%202015-04-24%2018%3A21%3A52.png?dl=0 >>> in >>> the scope, which seems quite chaotic and intractable. >>> >>> I hope you can give me some more details on how to use the qdr_transpose >>> block. Thanks! >>> >>> >>> >>> >>> On Thu, Mar 26, 2015 at 4:38 PM, Chenwei Cai <caichenwei1...@gmail.com> >>> wrote: >>> >>>> Dear CASPER, >>>> >>>> My name is Chenwei Cai, and I am constructing the Mega-Channel >>>> Spectrometer with ROACH II. To achieve that, two corner turners are >>>> required before we implement FFTs, which means I may use qdr_transpose or >>>> qdr_ct blocks. Since I cannot find any explanations on these blocks >>>> anywhere, could you provide me some details about the functions of these >>>> two blocks and what kind of data do those ports receive/export? >>>> >>>> Look forward to hearing from you! >>>> >>>> -- >>>> Best Regards >>>> Chenwei CAI >>>> >>>> Mobile: +86-152-0147-9411 >>>> Email: caichenwei1...@pku.edu.cn >>>> >>>> >>> >>> >>> -- >>> Best Regards >>> Chenwei CAI >>> >>> Mobile: +86-152-0147-9411 >>> Email: caichenwei1...@pku.edu.cn >>> >>> > > > -- > Best Regards > Chenwei CAI > > Mobile: +86-152-0147-9411 > Email: caichenwei1...@pku.edu.cn > >
