Further, is the board clocking OK? -- I believe the initialization script
should give feedback on whether of not the FPGA's PLL has successfully
locked to the ADC clock, and what the current measured board clock is.

Cheers
Jack

On Wed, 29 Mar 2017 at 14:28 Matt Dexter <mdex...@berkeley.edu> wrote:

> Is the design and lab setup consistent with the limitations documented at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
> ?
>
> More information on the clock requirements may be found at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs
>
> Matt
>
> On Wed, 29 Mar 2017, vijay kumar wrote:
>
> > Date: Wed, 29 Mar 2017 17:16:34 -0400
> > From: vijay kumar <vijaykumar01031...@gmail.com>
> > To: casper@lists.berkeley.edu
> > Subject: [casper] ADC calibration issue
> >
> > Hello Casperites,
> > I have been working on the ROACH-2 casper for the past few months. Now i
> have started to capture values from the ADC
> > 16x250-8 block. But, when I am trying to run the initialization script,
> it gives me an error saying that "chip 'x'
> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
> might be causing this error. I would be glad
> > if I could get help from you guys.
> >
> > Thank you.
> >
> >
> > With regards
> > Vijay
> >
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