Hi All, I've abandoned my attempt to use the DRAM for now and moved on to QDR. I'm somewhat confused by the wiki at https://casper.berkeley.edu/wiki/Qdr .
The "issuing commands section" says that one type of command cannot be issued in two consecutive cycles. The "bursting" section says that data for both read and write is presented for two cycles, and that data_in and be must be set for both of those cycles. Does this mean that a "write event" lasts for two clock cycles? If so, can data_in change from the first clock cycle to the second, storing a total of 144 bits over two cycles? Thanks, --Adam ---------------------------------------------------- Adam Schoenwald - Electrical Engineer ---------------------------------------------------- -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
