OK, here is try 2, with changes per your comments.
qemu boots fine. I appreciate all the comments!
I think we're close.
Thanks
ron
This is not signed off yet, but is close.
It also boots qemu just fine, which is a good sign.
Note that from now on, to pull a constructor into the coreboot image and
make it available, some dts somewhere has to name it.
I am almost certain we can now completely remove all the domainid, pciid, and
such ugly stuff.
Comments welcome.
Index: southbridge/amd/cs5536/cs5536.c
===================================================================
--- southbridge/amd/cs5536/cs5536.c (revision 592)
+++ southbridge/amd/cs5536/cs5536.c (working copy)
@@ -644,11 +644,8 @@
.phase6_init = southbridge_init,
};
-struct constructor cs5536_constructors[] = {
- {.id = {.type = DEVICE_ID_PCI,
+struct constructor cs5536_constructor = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
- .ops = &southbridge_ops},
-
- {.ops = 0},
-};
+ .ops = &southbridge_ops};
Index: southbridge/amd/cs5536/dts
===================================================================
--- southbridge/amd/cs5536/dts (revision 592)
+++ southbridge/amd/cs5536/dts (working copy)
@@ -19,8 +19,7 @@
*/
{
- constructor = "cs5536_constructors";
- pciid = "PCI_VENDOR_ID_AMD,PCI_DEVICE_ID_AMD_CS5536_ISA";
+ constructor = "cs5536_constructor";
/* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0";
Index: southbridge/intel/i82371eb/ide
===================================================================
--- southbridge/intel/i82371eb/ide (revision 592)
+++ southbridge/intel/i82371eb/ide (working copy)
@@ -21,5 +21,5 @@
{
ide0_enable = "0";
ide1_enable = "0";
- constructor = "i82371eb_constructors";
+ constructor = "i82371eb_ide";
};
Index: southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- southbridge/intel/i82371eb/i82371eb.c (revision 592)
+++ southbridge/intel/i82371eb/i82371eb.c (working copy)
@@ -116,15 +116,18 @@
.ops_pci = &pci_dev_ops_pci,
};
-struct constructor i82371eb_constructors[] = {
- {.id = {.type = DEVICE_ID_PCI,
+struct constructor i82371eb_isa = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7000}}},
- &i82371eb_isa_ops_dev},
- {.id = {.type = DEVICE_ID_PCI,
+ &i82371eb_isa_ops_dev};
+
+struct constructor i82371eb_ide = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7010}}},
- &i82371eb_ide_ops_dev},
- {.id = {.type = DEVICE_ID_PCI,
+ &i82371eb_ide_ops_dev};
+
+struct constructor i82371eb_acpi = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7113}}},
- &i82371eb_acpi_ops_dev},
- {.ops = 0},
-};
+ &i82371eb_acpi_ops_dev};
+
Index: southbridge/intel/i82371eb/dts
===================================================================
--- southbridge/intel/i82371eb/dts (revision 592)
+++ southbridge/intel/i82371eb/dts (working copy)
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-{
- ide0_enable = "0";
- ide1_enable = "0";
- constructor = "i82371eb_constructors";
-};
Index: mainboard/pcengines/alix1c/dts
===================================================================
--- mainboard/pcengines/alix1c/dts (revision 592)
+++ mainboard/pcengines/alix1c/dts (working copy)
@@ -22,26 +22,17 @@
enabled;
mainboard-vendor = "PC Engines";
mainboard-name = "ALIX1.C";
- cpus {
- enabled;
- };
- apic {
+ cpus { };
+ [EMAIL PROTECTED] {
/config/("northbridge/amd/geodelx/apic");
- enabled;
};
- domain0 {
+ [EMAIL PROTECTED] {
/config/("northbridge/amd/geodelx/domain");
- enabled;
- pcidomain = "0";
- device0,0 {
- /config/("northbridge/amd/geodelx/pci");
- enabled;
- pcipath = "1,0";
+ [EMAIL PROTECTED],0 {
+ /config/("northbridge/amd/geodelx/pci");
};
- southbridge {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
- pcipath = "0xf,0";
- enabled;
enable_ide = "1";
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -54,7 +45,7 @@
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
};
- superio {
+ [EMAIL PROTECTED] {
/config/("superio/winbond/w83627hf/dts");
com1enable = "1";
};
Index: mainboard/emulation/qemu-x86/dts
===================================================================
--- mainboard/emulation/qemu-x86/dts (revision 593)
+++ mainboard/emulation/qemu-x86/dts (working copy)
@@ -24,12 +24,12 @@
constructor = "qemuvga_constructors";
cpus {};
[EMAIL PROTECTED] {
- /config/("northbridge/intel/i440bxemulation/dts");
+ /config/("northbridge/intel/i440bxemulation/domain");
[EMAIL PROTECTED] {
[EMAIL PROTECTED],0 {
};
[EMAIL PROTECTED],0 {
- /config/("southbridge/intel/i82371eb/dts");
+ /config/("southbridge/intel/i82371eb/ide");
};
};
};
Index: device/device.c
===================================================================
--- device/device.c (revision 592)
+++ device/device.c (working copy)
@@ -123,13 +123,12 @@
for (i = 0; all_constructors[i]; i++) {
printk(BIOS_SPEW, "%s: check all_constructors[i] %p\n",
__func__, all_constructors[i]);
- for (c = all_constructors[i]; c->ops; c++) {
- printk(BIOS_SPEW, "%s: cons %p, cons id %s\n",
- __func__, c, dev_id_string(&c->id));
- if (id_eq(&c->id, id)) {
- printk(BIOS_SPEW, "%s: match\n", __func__);
- return c;
- }
+ c = all_constructors[i];
+ printk(BIOS_SPEW, "%s: cons %p, cons id %s\n",
+ __func__, c, dev_id_string(&c->id));
+ if (id_eq(&c->id, id)) {
+ printk(BIOS_SPEW, "%s: match\n", __func__);
+ return c;
}
}
Index: northbridge/amd/geodelx/domain
===================================================================
--- northbridge/amd/geodelx/domain (revision 592)
+++ northbridge/amd/geodelx/domain (working copy)
@@ -19,7 +19,6 @@
*/
{
- constructor = "geodelx_north_constructors";
- domainid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+ constructor = "geodelx_north_domain";
};
Index: northbridge/amd/geodelx/geodelx.c
===================================================================
--- northbridge/amd/geodelx/geodelx.c (revision 592)
+++ northbridge/amd/geodelx/geodelx.c (working copy)
@@ -354,24 +354,23 @@
* The constructor for the device.
* Domain ops and APIC cluster ops and PCI device ops are different.
*/
-struct constructor geodelx_north_constructors[] = {
+struct constructor geodelx_north_domain = {
/* Northbridge running a PCI domain. */
- {.id = {.type = DEVICE_ID_PCI_DOMAIN,
+ .id = {.type = DEVICE_ID_PCI_DOMAIN,
.u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.ops = &geodelx_pcidomain_ops},
+ geodelx_north_apic = {
/* Northbridge running an APIC cluster. */
- {.id = {.type = DEVICE_ID_APIC_CLUSTER,
+ .id = {.type = DEVICE_ID_APIC_CLUSTER,
.u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.ops = &geodelx_apic_ops},
/* Northbridge running a PCI device. */
- {.id = {.type = DEVICE_ID_PCI,
+ geodelx_north_pci = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
- .ops = &geodelx_pci_ops},
-
- {.ops = 0},
-};
+ .ops = &geodelx_pci_ops};
Index: northbridge/amd/geodelx/pci
===================================================================
--- northbridge/amd/geodelx/pci (revision 592)
+++ northbridge/amd/geodelx/pci (working copy)
@@ -19,7 +19,6 @@
*/
{
- constructor = "geodelx_north_constructors";
- pciid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+ constructor = "geodelx_north_pci";
};
Index: northbridge/amd/geodelx/apic
===================================================================
--- northbridge/amd/geodelx/apic (revision 592)
+++ northbridge/amd/geodelx/apic (working copy)
@@ -19,7 +19,6 @@
*/
{
- constructor = "geodelx_north_constructors";
- apicid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+ constructor = "geodelx_north_apic";
};
Index: northbridge/intel/i440bxemulation/domain
===================================================================
--- northbridge/intel/i440bxemulation/domain (revision 592)
+++ northbridge/intel/i440bxemulation/domain (working copy)
@@ -20,6 +20,6 @@
{
ramsize = "128";
- constructor = "i440bx_constructors";
+ constructor = "i440bx_domain";
domainid = "0x8086, 0x7190";
};
Index: northbridge/intel/i440bxemulation/dts
===================================================================
--- northbridge/intel/i440bxemulation/dts (revision 592)
+++ northbridge/intel/i440bxemulation/dts (working copy)
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-{
- ramsize = "128";
- constructor = "i440bx_constructors";
- domainid = "0x8086, 0x7190";
-};
Index: northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- northbridge/intel/i440bxemulation/i440bx.c (revision 593)
+++ northbridge/intel/i440bxemulation/i440bx.c (working copy)
@@ -53,7 +53,7 @@
struct device *mc_dev;
u32 tolmk; /* Top of low mem, Kbytes. */
int idx;
- struct northbridge_intel_i440bxemulation_dts_config *device_configuration =
+ struct northbridge_intel_i440bxemulation_domain_config *device_configuration =
dev->device_configuration;
tolmk = device_configuration->ramsize * 1024;
mc_dev = dev->link[0].children;
@@ -66,7 +66,7 @@
/* Here are the operations for when the northbridge is running a PCI domain. */
/* See mainboard/emulation/qemu-x86 for an example of how these are used. */
-struct device_operations i440bxemulation_pcidomainops = {
+static struct device_operations i440bxemulation_pcidomainops = {
.constructor = default_device_constructor,
.phase3_scan = pci_domain_scan_bus,
.phase4_read_resources = pci_domain_read_resources,
@@ -79,12 +79,13 @@
/* The constructor for the device. */
/* The plain PCI device uses the standard PCI operations. */
-struct constructor i440bx_constructors[] = {
- {.id = {.type = DEVICE_ID_PCI_DOMAIN,
+struct constructor i440bx_domain = {
+ .id = {.type = DEVICE_ID_PCI_DOMAIN,
.u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
- .ops = &i440bxemulation_pcidomainops},
- {.id = {.type = DEVICE_ID_PCI,
+ .ops = &i440bxemulation_pcidomainops};
+
+struct constructor i440bx_pci = {
+ .id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7190}}},
- .ops = &default_pci_ops_bus},
- {.ops = 0},
-};
+ .ops = &default_pci_ops_bus};
+
Index: util/dtc/flattree.c
===================================================================
--- util/dtc/flattree.c (revision 593)
+++ util/dtc/flattree.c (working copy)
@@ -556,7 +556,7 @@
path);
}
if (!strncmp(tree->name, "lpc", 3)){
- fprintf(f, "\t.path = {.type=DEVICE_PATH_SUPERIO,.u={.superio={.iobase=%s}}},\n",
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_LPC,.u={.lpc={.iobase=%s}}},\n",
path);
}
}
@@ -727,13 +727,13 @@
/* find any/all properties with the name constructor */
for_each_config(tree, prop) {
if (streq(prop->name, "constructor")){
- printf("\t%s,\n", prop->val.val);
+ printf("\t&%s,\n", prop->val.val);
}
}
for_each_property(tree, prop) {
if (streq(prop->name, "constructor")){
- printf("\t%s,\n", prop->val.val);
+ printf("\t&%s,\n", prop->val.val);
}
}
@@ -790,13 +790,13 @@
for_each_config(tree, prop) {
if (! streq(prop->name, "constructor")) /* this is special */
continue;
- fprintf(f, "extern struct constructor %s[];\n", prop->val.val);
+ fprintf(f, "extern struct constructor %s;\n", prop->val.val);
}
for_each_property(tree, prop) {
if (! streq(prop->name, "constructor")) /* this is special */
continue;
- fprintf(f, "extern struct constructor %s[];\n", prop->val.val);
+ fprintf(f, "extern struct constructor %s;\n", prop->val.val);
}
for_each_property(tree, prop) {
--
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