Le 15/12/13 16:03, Toru Nishimura a écrit :
Yann Sionneau commentted a whole ago;
instead of frequently do a ASID_FLUSH which is basically
stalling the CPU pipeline while iterating over the whole TLB
which takes something like 2*1024 clock cycles :)
That's one of the reason why most commercial CPUs have
rather small TLB whose size is upto 32 entries or so, I think.
That's a rather interesting optimization I didn't think about :)
Thanks Werner and Toru!
Cheers,
--
Yann Sionneau
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