Hi,
My impression is it'd be not a good idea to hold ASID value or other TLB
control stuff in PSW. I do understand what MIPS eret insn, which happens
be the very same name in LM32, does. eret "return from exception" should
have nothing to do with TLB runtime. Then your trouble is made by a design
mistake to combine ASID / TLB with PSW management.
I would propose to extend LM32 rcsr/wcsr insns to have a lot more custom
CSR registers. LM32 has only 5bit for CSR. 5 bit is away too small. Other
CPUs have much more space to have control registers, e.g., PPC allows
beyond 1024 SPRs (special purpose registers) which is in turn an infamous
reason why IBM PPC and Moto PPC have similar-but-different-in-detail SPRs
in parallel :-{
xrcsr (r31 = 1.1111) to mark extention; use LSB field for custom CSRs.
xwcsr (r31 = 1.1111) to mark extention; use LSB field for custom CSRs.
Toru Nishimura / Bangalore India 560078 / ALKYL Technology
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