For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases only where pipe_bpp is to be computed.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 46 ++++++++++++++++---------
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d828ea0894d..d061fc3fa402 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1480,6 +1480,13 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ /* Min Input BPC for ICL+ is 8 */
+ return (pipe_bpp < 8 * 3);
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1491,7 +1498,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1501,27 +1507,35 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return -EINVAL;
if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
pipe_bpp);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ int forced_bpc = intel_dp->force_dsc_bpc;
+ int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
- return -EINVAL;
+ /* Min Input BPC for ICL+ is 8 */
+ if (forced_bpc < 8) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Cannot force dsc bpc:%d, due to dsc bpc
limits\n",
+ intel_dp->force_dsc_bpc);
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
+ pipe_config->pipe_bpp);
+ } else if (compute_pipe_bpp) {
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+
conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No DSC support for less than 8bpc\n");
+ return -EINVAL;
+ }
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1544,7 +1558,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
- pipe_bpp,
+
pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.25.1
