Currently the required dsc output bpp is set to be the largest
compressed bpp supported for max, lane, rate, and bpp.
The helper intel_dp_dsc_get_output_bpp gets the maximum supported
compressed bpp taking into account link configuration, input bpp,
bigjoiner considerations etc.
Similarly, the helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the functions to reflect that these return max DSC input and
output bpps.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++----
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c52e9979f0a4..c0b96cfb7528 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -702,12 +702,12 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct
drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1030,7 +1030,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be
picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
@@ -1040,13 +1040,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1375,7 +1375,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
return -EINVAL;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1518,7 +1518,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp = forced_bpp;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp,
conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
@@ -1548,14 +1548,14 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (compute_pipe_bpp) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
-
pipe_config->port_clock,
-
pipe_config->lane_count,
-
adjusted_mode->crtc_clock,
-
adjusted_mode->crtc_hdisplay,
-
pipe_config->bigjoiner_pipes,
-
pipe_config->pipe_bpp,
- timeslots);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+
pipe_config->port_clock,
+
pipe_config->lane_count,
+
adjusted_mode->crtc_clock,
+
adjusted_mode->crtc_hdisplay,
+
pipe_config->bigjoiner_pipes,
+
pipe_config->pipe_bpp,
+ timeslots);
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index ef39e4f7a329..7cb8227a4d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -102,13 +102,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp,
- u32 timeslots);
+int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5b65e4c2c78f..df19691776ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -911,17 +911,17 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector
*connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be
picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- pipe_bpp, 64);
+ intel_dp_dsc_get_output_bpp_max(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.25.1
