EBo wrote: > On Fri, 18 May 2012 18:42:53 -0700, dave wrote: > >> Matt and I were talking the other day about a next-gen linuxcnc >> processor and wandered into the area of a decent processor coupled to >> an fpga for all the stuff that a normal processor doesn't do well. >> > > have you taken a look at Yishin Li's work through www.araisrobo.com? I > hope to start playing with this soon. > I was sure hoping that the Beagle Board would be the CPU part, and I could make a board that hooked to the GPIO expansion header for the FPGA part. The only holdup is the RT problem.
One surprise I found was that the GPIO on the Beagle Board's OMAP CPU is multiplexed, and on the original 600 MHz processor you could only update a pin every 240 ns. As best as I could tell, the CPU went into a wait state during the time it took for the GPIO pin to update. This not only limited the I/O rate, it also dramatically slowed down the CPU. On the other hand, examining latency via oscilloscope showed the thing to be astoundingly regular just in user mode. This multiplexing is not described ANYWHERE in the 3700!! page technical doc on the CPU. Does anyone know if this multiplexing is standard on all ARM CPUs or is just on some, like the OMAP used on the Beagle? (I think it is an OMAP3430, but not completely sure of the model #.) If all the I/O pads ran even a little closer to CPU speed, it would be a big help! On the Beagle, it seems the GPIO updates every 140 CPU clock cycles. Jon ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
