Charles Steinkuehler wrote:
> My current plan is to bit-bang GPIO pins based on code from the
> parallel port driver, but adding a bit of electronics would probably
> make things much easier. I'll evaluate that option once I see where I
> get with software stepgen.
>
Well, it totally depends on the latency performance of whatever kernel
you are
using. RTAI when it is good is OK for software step generation, but just
barely, unless you are satisfied with very slow motion. I've seen some
comments that seem to suggest 100 us latencies might be about as good as it
gets on ARM processors with the preempt-RT kernel.
I'm also hoping on the Arm it might be possible to use the fast IRQ
and read/write the I/O pins in an ISR which may allow the servo thread
to run with much higher jitter.
This is unlikely to help any, as that is basically what an RT task is, a
thread that runs
several kernel modules in response to an interrupt.
Jon
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
_______________________________________________
Emc-developers mailing list
Emc-developers@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/emc-developers
