Well, I'm in BIG trouble. I have 3 PCIe parallel port cards here that are all doing the same thing. They are, however, all the exact SAME PC board with the Oxford OXPCIe952 chip. They are branded SIIG, Startech and Rosewill. I cannot get them to work with my PPMC-family boards. I hooked up the logic analyzer, and my diagnostic program does a series of writes to the board that all look OK. Then, it tries to enumerate the board, and this involves an address write and then a data read, and the read is not performed at ALL. (The data writes performed previously all look fine, WRITE/ is asserted with the data lines, then DATASTB/ is pulsed and WAIT/ acknowledges the cycle.) For the reads, WRITE/ goes low with the address to be read on the data lines, ADDRSTB/ is pulsed, WAIT/ acknowledges it. THEN, WRITE/ is supposed to stay high, and DATASTB/ SHOULD be pulsed, but NOTHING happens!
The only thing I can figure is that the reconfiguration I've been using for well over a DECADE to turn the bus from write mode to read mode has somehow disabled the EPP data cycle. As far as I know, the way I'm doing this is approved and recommended by all the experts who have written how to do EPP transfers at the PC register level. Setting the port to write mode : write 0x04 to controlport Setting the port to read mode : OR 0x20 to controlport Anybody ever done EPP programming that might have some ideas? Jon ------------------------------------------------------------------------------ Find and fix application performance issues faster with Applications Manager Applications Manager provides deep performance insights into multiple tiers of your business applications. It resolves application problems quickly and reduces your MTTR. Get your free trial! http://pubads.g.doubleclick.net/ gampad/clk?id=1444514301&iu=/ca-pub-7940484522588532 _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
