Good suggestion. Add the testcase.
thanks
Guozhi Wei
2014-08-20 Guozhi Wei <car...@google.com>
PR target/62040
* gcc.target/aarch64/pr62040.c: New test.
Index: pr62040.c
===================================================================
--- pr62040.c (revision 0)
+++ pr62040.c (revision 0)
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+#include "arm_neon.h"
+
+extern bar(int32x4_t);
+
+void foo() {
+ int32x4x4_t rows;
+ uint64x2x2_t row01;
+
+ row01.val[0] = vreinterpretq_u64_s32(rows.val[0]);
+ row01.val[1] = vreinterpretq_u64_s32(rows.val[1]);
+ uint64x1_t row3l = vget_low_u64(row01.val[0]);
+ row01.val[0] = vcombine_u64(vget_low_u64(row01.val[1]), row3l);
+ int32x4_t xxx = vreinterpretq_s32_u64(row01.val[0]);
+ int32x4_t out = vtrn1q_s32 (xxx, xxx);
+ bar(out);
+}
On Wed, Aug 20, 2014 at 4:26 AM, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote:
> Hi Carrot,
>
> cc'ing the aarch64 maintainers...
>
>
> On 20/08/14 00:43, Carrot Wei wrote:
>>
>> Hi
>>
>> Current AArch64 backend can generate rtl expressions like
>> (vec_duplicate:DI (const_int 0 [0])), which causes ICE in
>> simplify_const_unary_operation because vec_duplicate should generate
>> vector mode only.
>>
>> As suggested by Andrew in the bug entry, I split the original insn
>> patterns to avoid scalar mode vec_duplicate expression.
>
>
> The documentation does say that vec_concat can work on scalars, so it seems
> ok to me at a glance (but I can't approve it myself).
>
> Would be nice to have an addition to the testsuite though...
>
> Kyrill
>
>
>> Passed regression tests on qemu without failure.
>> OK for trunk and 4.9 branch?
>>
>> thanks
>> Guozhi Wei
>>
>> 2014-08-19 Guozhi Wei <car...@google.com>
>>
>> PR target/62040
>> * config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
>> * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>):
>> Split
>> it into two patterns.
>> (move_lo_quad_internal_be_<mode>): Likewise.
>
>
>
