You want to mark them nonspeculative too. Generally speaking, you can't undo a speculative update to a miscreg.
Gabe On 05/30/11 16:23, Ali Saidi wrote: > Korey is pretty much correct. The miscellaneous registers are read at > any time, but they're only written at commit. So if you're updating > the state in some way that effects future instructions the code that > does the update must be marked IsSerializeAfter which prevents any > future instructions from issuing until the current one commits. > > Ali > > > On May 29, 2011, at 11:49 PM, Korey Sewell wrote: > >> >> If you don't mind my asking, how is this made safe? Is it some >> form of speculation? >> >> Misc. registers refer to non-speculative system state, so any >> instruction that is going to change these is typically marked with a >> Serializing or IsNonSpeculative flag. >> >> The CPU Models can then treat these type of instructions >> appropriately. For the O3, I think it will wait to the instruction >> reaches the head of the ROB to eventually execute and commit it. >> >> Can you track the path of that instruction in O3 to confirm that? >> -- >> - Korey >> _______________________________________________ >> gem5-users mailing list >> gem5-users@m5sim.org <mailto:gem5-users@m5sim.org> >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > gem5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
