It was changed maybe 6 months ago. All writes to misc registers are
always buffered until commit and then written when the instruction
becomes non-speculative. This is how the exception sticky flags work for
example. Otherwise every instruction that set one of these sticky flags
in ARM would need to execute after anything that previously set them and
do a rmw on the flag(which wouldn't perform well at all).
Ali
On Tue, 31 May 2011 16:55:46 -0400, Gabriel Michael Black
<gbl...@eecs.umich.edu> wrote:
I think that's -why- it's not written until commit, unless that
changed recently. The serialization support makes instructions wait
after decode, I think, until the serializing instruction commits.
Gabe
Quoting Ali Saidi <sa...@umich.edu>:
That actually isn't required. Since the update only happens at
commit
the instruction is non-speculative at that point in time.
Ali
On
Mon, 30 May 2011 19:12:50 -0700, Gabe Black wrote: You want to
mark
them nonspeculative too. Generally speaking, you can't undo a
speculative update to a miscreg.
Gabe
On 05/30/11 16:23, Ali Saidi
wrote:
Korey is pretty much correct. The miscellaneous registers are
read at any time, but they're only written at commit. So if you're
updating the state in some way that effects future instructions the
code
that does the update must be marked IsSerializeAfter which prevents
any
future instructions from issuing until the current one commits.
Ali
On May 29, 2011, at 11:49 PM, Korey Sewell wrote:
If you don't mind
my asking, how is this made safe? Is it some form of speculation?
Misc. registers refer to non-speculative system state, so any
instruction that is going to change these is typically marked with a
Serializing or IsNonSpeculative flag.
The CPU Models can then treat
these type of instructions appropriately. For the O3, I think it
will
wait to the instruction reaches the head of the ROB to eventually
execute and commit it.
Can you track the path of that instruction in
O3 to confirm that? --
- Korey
_______________________________________________
gem5-users mailing
list
gem5-users@m5sim.org
[1]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]
_______________________________________________ gem5-users mailing
list
gem5-users@m5sim.org [3]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [4]
Links:
------
[1] mailto:gem5-users@m5sim.org
[2]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[3]
mailto:gem5-users@m5sim.org
[4]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@m5sim.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@m5sim.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users