I have also been thinking about the same issue with bus being a bottleneck.
And I know that with the Ruby memory model we can use other interconnects,
but I think that only works for the timing cpu. I am particularly interested
in O3 and inorder cpu models. Is there a way we can address this issue in
the O3 and inorder cpu by using the current Bus infrastructure ? Is it
possible to have a point to point network model using O3 and/or inorder
cpus.

On Wed, Jun 8, 2011 at 12:30 PM, Gabe Black <gbl...@eecs.umich.edu> wrote:

>  That's the whole bus bandwidth. It could very well limit performance
> depending on its properties and how it's integrated into the system.
>

Also, what did you mean by - "depending on how it's integrated to the
system"? Is there any other way you can integrate a bus except for how it is
done in the default configuration scripts.


>
> Gabe
>
>
> On 06/08/11 08:56, Dawei Wang wrote:
>
> Hello, everyone
>
>  Now I am simulating M5 with more than 16 cores. Each core has its private
> L1 I&D cache, and every L1 cache share one big L2 cache.
> My question is when the number of cores become larger and larger, will the
> tol2bus become the whole system bottleneck?
>
>  I have seen the bus.hh and Bus.py. I know the default configuration is
> 1GHz and 64 Byte width. But I didn't see any bus arbitration. So the 64GB/s
> is whole bus bandwidth, or any peer-to-peer link bandwidth. Therefore, I
> wonder whether the tol2bus will become performance limiter?
>
>
>  Many thanks in advance.
> Dawei
>
>
> _______________________________________________
> gem5-users mailing 
> listgem5-users@m5sim.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
>
> _______________________________________________
> gem5-users mailing list
> gem5-users@m5sim.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>



-- 
-Abhishek

Graduate Student
Computer Science
University of Virginia

---------------------------------------------------------------------------------------------------------------------
simplicity is the ultimate sophistication
-Leonardo da Vinci
_______________________________________________
gem5-users mailing list
gem5-users@m5sim.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to