Thank you Joost!
I have read through the section from GNU make manual and it answered my question. Cool! regards, George --- "Leeuwesteijn,Joost" <[EMAIL PROTECTED]> wrote: > Hi George, > > > -------------------- > > Goo: > > @echo "Goo" > > > > Foo: Goo > > > > Foo: > > @echo "Foo" > > -------------------- > > when I execute make Foo, the output is, > > -------------------- > > Goo > > Foo > > -------------------- > > So, my question is that. Is it ok to define a > target more > > than once? Always ok or under some conditions? > > Check the manual :-) Chapter 4.10 Multiple Rules for > One Target (version > 3.81). > > 'Foo : Goo' just adds a prerequisite to Foo. The > actual command/recipe is > defined in the last Foo rule. This can be used to > add dependencies for > example. I use: > foo.o : foo.c > @build foo > > and then I also include a makefile that contains: > foo.o : foo.h bar.h > > This is the same as: > foo.o : foo.c foo.h bar.h > > Regards, > Joost Leeuwesteijn > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
