Thanks to all of those that are replying. I've found a wealth of information in the IBM R&D website. They have an issue that details the architecture of the z990 CPU very clearly. It seems as through IBM is modernizing the arch to handle more OOE/Superscalar execution as they make a push to SOA and e-business models. Out of curiosity, I've started poking around the system I've access to through ISPF to find out more regarding the hardware. Through the ISPVCALL STATUS function, I found that the system I'm on is a zArch 2064 with 4 CPUs; however, is there a way I can retrieve the model # of this system as well?
-----Original Message----- From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] Behalf Of Tom Marchant Sent: Wednesday, July 19, 2006 10:35 AM To: IBM-MAIN@BAMA.UA.EDU Subject: Re: Newbie Questions! On Tue, 18 Jul 2006 15:46:27 -0400, Kuredjian, Michael <[EMAIL PROTECTED]> wrote: >I'm currently in University on my Co-op term as a COBOL programmer for host systems (zOS). I have a few basic questions regarding the zArchitecture that I can't seem to elicit answers to from my co-workers. The questions are as follows: > >1. zOS has a kernel called the BCP, or Base Control Program. In Linux >or Windows, it's established that the kernel runs on a general purpose >CPU( PowerPC, x86, MIPS, etc...); however, I would like to know if >such a central CPU exists in the mainframe, and if that central CPU >is of some common architecture like, POWER. If not, are there any >documents that I can look into that will describe the CPU >architecture for me? While the processor has been enhanced over the years, the CPU may be the first general purpose architecture still in existence. The 360 architecture is still an integral and important part of z/Architecture, and almost any program written for 360 will run without being modified on z/Architecture. > >2. ESCON and FICON are data busses used for external storage devices, >but what does the mainframe use for internal data bus, InfiniBand, >HyperTransport? IBM doesn't make the internal details available. In order to perform, there is a lot of point-to-point interconnect. Paths to memory are very wide, again to improve performance. I can't seem to find the last reference I found, but I think it's 256 bytes. FICON is essentially Fibre Channel with extra layers to improve security. > >3. Does the mainframe use common interconnects on the hardware level? >I'm thinking of PCIe, PCI-X, MCA, or PCI. AS someone mentioned, there are PCI slots for cryptographic processors, but for general use, none of those is fast enough. Connections from memory to the channels is through 16 Self Timed Interconnect (STI) busses per book (a maximum of 64), each of which is capable of independently transferring 2.7 Gigabytes per second. The z9 EC can support up to 336 FICON channels, and STI is how the data is transferred between the channels and memory. The channels on the mainframe do not talk directly to devices, but to control units, which are specialized processors that relieve the processor of the details of most of the workings of the device. There are tons of details on the IBM web site. Try these, for example: http://www-03.ibm.com/systems/z/hardware/ http://www-03.ibm.com/servers/eserver/zseries/zos/ Good luck, and welcome to the platform! Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
