Im having an issue getting my build system set up the way id like and im
hoping someone here can point me in a new direction or perhaps offer some
If i manually add each .o file i want built to the makefile the lkm will
build with no issues, essentially this works:

OBJS = main.o
#OBJS += wm_algo_common.o
#OBJS += wm_algomgr_ops.o
#OBJS += wm_algomgr_static.o
#OBJS += wm_algo_tcp1.o
#OBJS += wm_algo_tcp2.o
#OBJS += wm_algo_udp.o
#OBJS += wm_arp_reg_method.o
#OBJS += wmc_algomgr.o
#OBJS += wmc_core.o
#OBJS += wmc_core_function.o
#OBJS += wmc_debug.o
#OBJS += wmc_linked_list.o
#OBJS += wm_core_info.o
#OBJS += wm_core_ops.o
#OBJS += wmc_packet_common.o
#OBJS += wmc_regmgr.o wm_driver.o
#OBJS += wm_hashtable.o
#OBJS += wm_network_common.o
#OBJS += wm_regmgr_ops.o
#OBJS += wm_regmgr_static.o

Granted these are commented out but they will build a loadable lkm if i
un-comment the obj lines. What i would really like is just to be able to
drop new sources into my build directory and have the makefile pick them up
and build them auto-magically, something like this:

OBJS = $(patsubst %.c,%.o,$(wildcard $(PWD)/*.c))

Now, this should work because the makefile is in the same directory as the
sources/headers so it should pick up the .c files and substitute to the .o
files then i can build with my default target:

        @echo $(OBJS)
        $(MAKE) -C $(KDIR) M=$(PWD) PWD=$(PWD) V=1 modules

The issue is the echo statement looks fine but when the makefile switches
into the source one of two things happens depending on how i have the OBJS
line setup. If the objs line is setup like it is in second snipped; because
kbuild prefixes the PWD path to the directory where the makefile is stored
twice the build breaks, like this:

make[2]: *** No rule to make target

You can see the first
/home/chorlick/Code/watermarking/trunk/code/framework/build/linux/lkdm comes
from kbuild's prefix the second is the PWD path picked up from the wildcard
function in the makefile. This being the case i have tried using this line:

OBJS = $(patsubst %.c,%.o,$(wildcard *.c))

The problem here is that make cant find the sources because when that
variable get evaluated its off in the kernel sources build directory and of
course my code isnt located there. So in a nutshell does anyone know a way
to disable kbuild's path prefixing or a way to force kbuild to evaulate PWD
as something slightly different so i can just use the :

OBJS = $(patsubst %.c,%.o,$(wildcard *.c))


If anyone can point me to the "kbuild" way of doing things, it would be
greatly appreciated. Thanks!

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