Jeff V. Merkey wrote:
> One of the best references that describes the bus transaction model for
> Intel in "plain english" is the Pentium Pro Processor System
> Architecture Manual by Tom Shanley of Mindshare, Inc., Addison Wesley,
> ISBN: 0-201-47953-2. It explains a very good detail how the cache
> controllers and MESI works on Intel.
Agreed, it is a very informative book. More detail than you need unless
you're cloning the chips ;-) Full of good ideas, especially for anyone
interested in memory hierarchies.
> In NetWare, we didn't care if the page was touched or not since we
> used our own bits in field bits 11-9 to store page specific stuff,
> like whether the page was dirty or not.
Linux does actually look at both bits, but the optimisation still
applies. Accessed in particular -- ptes are mapped on page faults so
you know the page is about to be accessed.
> We saw a 4% performance improvement for Network I/O by avoiding the
> "hidden" locking in Intel's architecture. You should check if you need
> this bit, and if not, always create the PTE with it set. I don't know
> how much it would help Linux. NetWare is well optimized for Intel
> processors and any little thing that increased bus memory utilization
> was very noticeable on NetWare, since it supports such huge user loads
> already.
>
> :-)
Use Linux. Grok Linux. Read the source and weep :-)
But thanks for the tip :-)
Btw, any good tips you have on effective paging heuristics -- now they
_would_ be useful I'm sure. Linux paging is still rather experimental
after all these years. As in, it works but could do better.
-- Jamie
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