On 31/03/2017 4:30 AM, Alan Tull wrote:
On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao <hao...@intel.com> wrote:
From: Kang Luwei <luwei.k...@intel.com>
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).
This patch adds support for PR sub feature. In this patch, it registers
a fpga_mgr and implements fpga_manager_ops, and invoke fpga_mgr_buf_load
for PR operation once PR request received via ioctl. Below user space
interfaces are exposed by this sub feature.
Sysfs interface:
* /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/interface_id
Read-only. Indicate the hardware interface information. Userspace
applications need to check this interface to select correct green
bitstream format before PR.
Ioctl interface:
* FPGA_FME_PORT_PR
Do partial reconfiguration per information from userspace, including
target port(AFU), buffer size and address info. It returns the PR status
(PR error code if failed) to userspace.
Signed-off-by: Tim Whisonant <tim.whison...@intel.com>
Signed-off-by: Enno Luebbers <enno.luebb...@intel.com>
Signed-off-by: Shiva Rao <shiva....@intel.com>
Signed-off-by: Christopher Rauer <christopher.ra...@intel.com>
Signed-off-by: Alan Tull <alan.t...@intel.com>
Hi Wu Hao,
Thanks for submitting your patches.
I think there's been a misunderstanding of the meaning of
'Signed-off-by' [1]. I have not signed off on this code or had a hand
in its development. But I'm happy to get to review it now. It will
take a bit of time; I expect to be replying next week.
Hi Alan,
Sorry to confuse you, i think it's because you helped Chris a lot to
implement this interface and we'd like to include your credit as this
way. If you dislike, it will be dropped. :)
Thanks for your review in advance.
