[PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3

[Florian Fainelli]

The ARMv8 PMUv3 cache map did not include the L2 cache events, add
them.

Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
---
 arch/arm64/kernel/perf_event.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4f011cdd756d..a664c575f3fd 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -264,6 +264,11 @@ static const unsigned 
armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
        [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = 
ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 
+       [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+       [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = 
ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+       [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+       [C(LL)][C(OP_WRITE)][C(RESULT_MISS)]    = 
ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+
        [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = 
ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
        [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
 
-- 
2.9.3