On Fri, May 26, 2017 at 08:51:48AM -0700, Linus Torvalds wrote: > On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov > <kir...@shutemov.name> wrote: > > > > I don't see how kernel threads can use 4-level paging. It doesn't work > > from virtual memory layout POV. Kernel claims half of full virtual address > > space for itself -- 256 PGD entries, not one as we would effectively have > > in case of switching to 4-level paging. For instance, addresses, where > > vmalloc and vmemmap are mapped, are not canonical with 4-level paging. > > I would have just assumed we'd map the kernel in the shared part that > fits in the top 47 bits. > > But it sounds like you can't switch back and forth anyway, so I guess it's > moot. > > Where *is* the LA57 documentation, btw? I had an old x86 architecture > manual, so I updated it, but LA57 isn't mentioned in the new one > either.
It's in a separate white paper for now: https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf -- Kirill A. Shutemov
