Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4843376..e9856fe 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,34 @@
status = "disabled";
};
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt2712-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM>,
+ <&pericfg CLK_PERI_PWM0>,
+ <&pericfg CLK_PERI_PWM1>,
+ <&pericfg CLK_PERI_PWM2>,
+ <&pericfg CLK_PERI_PWM3>,
+ <&pericfg CLK_PERI_PWM4>,
+ <&pericfg CLK_PERI_PWM5>,
+ <&pericfg CLK_PERI_PWM6>,
+ <&pericfg CLK_PERI_PWM7>;
+ clock-names = "top",
+ "main",
+ "pwm1",
+ "pwm2",
+ "pwm3",
+ "pwm4",
+ "pwm5",
+ "pwm6",
+ "pwm7",
+ "pwm8";
+ status = "disabled";
+ };
+
i2c0: i2c@11007000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11007000 0 0x90>,
--
1.9.1
