> -----Original Message-----
> From: Guo Ren <guo...@kernel.org>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <anup.pa...@wdc.com>
> Cc: Palmer Dabbelt <pal...@sifive.com>; Albert Ou
> <a...@eecs.berkeley.edu>; linux-kernel@vger.kernel.org; Mike Rapoport
> <r...@linux.ibm.com>; Christoph Hellwig <h...@infradead.org>; Atish Patra
> <atish.pa...@wdc.com>; Gary Guo <g...@garyguo.net>; Paul Walmsley
> <paul.walms...@sifive.com>; linux-ri...@lists.infradead.org
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
>
> Hi Anup,
>
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?
I am testing this using hackbench.
Regards,
Anup
