Patch series adds support in Sierra driver to use external clock. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [2] v3 of the patch series can be found @ [3]
Changes from v3: 1) Instead of adding separate subnodes for each clock, just add #clock-cells in Sierra SERDES nodes and model the clocks. This is in alignment with Rob's comment for a different series [4] 2) Removed device tree changes from the series. Changes from v2: 1) Add depends on COMMON_CLK in Sierra 2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate patch 3) Disable clocks in Sierra driver remove Changes from v1: 1) Remove the part that prevents configuration if the SERDES is already configured and focus only on using external clock and the associated cleanups 2) Change patch ordering 3) Use exclusive reset control APIs 4) Fix error handling code 5) Include DT patches in this series (I can send this separately to DT MAINTAINER once the driver patches are merged) [1] -> http://lore.kernel.org/r/20201103035556.21260-1-kis...@ti.com [2] -> http://lore.kernel.org/r/20201222070520.28132-1-kis...@ti.com [3] -> http://lore.kernel.org/r/20201224111627.32590-1-kis...@ti.com [4] -> http://lore.kernel.org/r/20210108025943.ga1790...@robh.at.kernel.org Kishon Vijay Abraham I (13): phy: cadence: Sierra: Fix PHY power_on sequence phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function phy: cadence: cadence-sierra: Explicitly request exclusive reset control phy: cadence-torrent: Use a common header file for Cadence SERDES phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) phy: cadence: phy-cadence-sierra: Enable pll_cmnlc and pll_cmnlc1 clocks .../bindings/phy/phy-cadence-sierra.yaml | 17 +- drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 419 ++++++++++++++++-- drivers/phy/cadence/phy-cadence-torrent.c | 2 +- drivers/phy/ti/phy-j721e-wiz.c | 21 +- include/dt-bindings/phy/phy-cadence-torrent.h | 15 - include/dt-bindings/phy/phy-cadence.h | 20 + 7 files changed, 428 insertions(+), 67 deletions(-) delete mode 100644 include/dt-bindings/phy/phy-cadence-torrent.h create mode 100644 include/dt-bindings/phy/phy-cadence.h -- 2.17.1
