On Mon, 10 Oct 2011, Jean Pihet wrote:
> On Fri, Oct 7, 2011 at 6:17 AM, Paul Walmsley <p...@pwsan.com> wrote:
> > On Wed, 21 Sep 2011, jean.pi...@newoldbits.com wrote:
> >
> >> From: Jean Pihet <j-pi...@ti.com>
> >>
> >> Figures are added to the power domains structs for RET and OFF modes.
> >>
> >> Note: the latency figures for MPU, PER, CORE, NEON have been obtained
> >> from actual measurements.
> >> The latency figures for the other power domains are preliminary and
> >> shall be added.
> >>
> >> Cf.
> >> http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement
> >> for a detailed explanation on where are the numbers magically coming from.
> >>
> >> Tested on OMAP3 Beagleboard in RET/OFF using wake-up latency constraints
> >> on MPU, CORE and PER.
> >
> > Do the CSWR measurements include the time for the PMIC to scale the
> > voltage, or do they just represent the time to enter and exit clock stop
> > (presumably with DPLL idling)?
>
> As described at [1] the measurements have not been performed with
> sys_offmode and sys_clkreq signals toggling correctly, because of the
> lack of support for it in the kernel.
> However the results are including a correction for the sys_offmode
> transition time (11.5ms), but no correction for the sys_clkreq signal
> (which should be 1ms for sysclk on, 2.5ms for sysclk off).
>
> [1]
> http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement#cpuidle_results
OK. sys_offmode only applies to OFF mode. Voltage scaling can also occur
during RETENTION and INACTIVE ("sleep"). So were these results with
retention and voltage scaling disabled?
- Paul
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