On 10/7/2015 12:20 PM, Christoph Hellwig wrote:
On Tue, Oct 06, 2015 at 11:37:40AM +0300, Sagi Grimberg wrote:
The issue is that the device requires the MR page array to have
an alignment (0x40 for mlx4 and 0x400 for mlx5). When I modified the
page array allocation to be non-coherent I didn't take care of
alignment.
Just curious: why did you switch away from the coheret dma allocations
anyway? Seems like the page lists are mapped as long as they are
allocated so the coherent allocator would seem like a nice fit.
Bart suggested that having to sync once for the entire page list might
perform better than coherent memory. I'll settle either way since using
non-coherent memory might cause higher-order allocations due to
alignment, so it's not free-of-charge.
Sagi.
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