On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
> Exynos4x12 has the following AXI buses to translate data between
> DRAM and sub-blocks.
>
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock for CAM/TV/LCD
> : The minimum clock of ACLK160 should be over 160MHz.
> When drop the clock under 160MHz, show the broken image.
> - ACLK133 clock for FSYS
> - GDL clock for LEFTBUS
> - GDR clock for RIGHTBUS
> - SCLK_MFC clock for MFC
>
> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
> ---
> arch/arm/boot/dts/exynos4x12.dtsi | 112
> ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 112 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
> b/arch/arm/boot/dts/exynos4x12.dtsi
> index 3bcf0939755e..8bc4aee156b5 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -354,6 +354,118 @@
> opp-microvolt = <950000>;
> };
> };
> +
> + bus_leftbus: bus_leftbus {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DIV_GDL>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_leftbus_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_rightbus: bus_rightbus {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DIV_GDR>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_leftbus_opp_table>;
> + status = "disabled";
> + };
These two nodes are symmetrical. The MFC below and other buses in other
DTS share opps. How about changing the binding so multiple clocks could
be specified at once ("bus0", "bus1")? I think there is no need for a
bus device for each clock.
Best regards,
Krzysztof
> +
> + bus_display: bus_display {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_ACLK160>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_display_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_fsys: bus_fsys {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_ACLK133>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_fsys_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_peri: bus_peri {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_ACLK100>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_peri_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_mfc: bus_mfc {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_SCLK_MFC>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_leftbus_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_leftbus_opp_table: opp_table3 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp00 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <900000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <134000000>;
> + opp-microvolt = <925000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <160000000>;
> + opp-microvolt = <950000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <1000000>;
> + };
> + };
> +
> + bus_display_opp_table: opp_table4 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp00 {
> + opp-hz = /bits/ 64 <160000000>;
> + opp-microvolt = <950000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <1000000>;
> + };
> + };
> +
> + bus_fsys_opp_table: opp_table5 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp00 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <900000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <134000000>;
> + opp-microvolt = <925000>;
> + };
> + };
> +
> + bus_peri_opp_table: opp_table6 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp00 {
> + opp-hz = /bits/ 64 <50000000>;
> + opp-microvolt = <900000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <925000>;
> + };
> + };
> };
>
> &combiner {
>
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