On Thu, Mar 02, 2000 at 01:40:55PM -0500, George Woltman wrote:
>The new SIMD2 instructions have the potential of doubling throughput.
But why would Intel market these instructions as `multimedia' instructions?
Surely no normal MM tasks would need double precision. Of course, I
shouldn't complain :-)
>The FXCH instruction is no longer free.
Is SIMD2 (or SSE2, or whatever Intel likes to call it) _still_ stack-based?
I thought Intel should have learned by now?
By the way, if the registers are not aliased upon the FP registers, what will
Intel do with the task switch problem? Back when MMX was new, I heard the
reason for aliasing the MMX registers upon the FP registers was that no OS
change would be neccessary (to save/restore the registers).
>Mispredicted branch penalties are higher, etc. etc.
Any idea why? BTW, branching when there is two different sets of code (running
in parallel) to take care of will be quite interesting :-)
/* Steinar */
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