Hi everyone!
I have found the problem and finished the script.
As you probably have more experience and insight, would it be
desireable to put this script into the reset init handler?
I have modified the lpc1768.cfg so that the flash's clock speed is
updated to 100MHz, and added the code needed to initialize the PLL to
100MHz. So in case of programming the device we can use clock speeds
up to 16 666Khz, which - based on the new mpsse driver - can achieve
write speeds of 75-100KB/s, and read speeds around 400K!
I'll have to look into how to use gerrit, and I would post the patch,
if you aggree it is.
You can see my script below. I'm sure someone with more experience can
change the "sleep 50" instructions to really poll the register for the
ready bit, but this works fine as it is, and 50ms is not that much
echo "Initialize PLL to 100MHz"
mww 0x400fc1a0 0x00000000;
mww 0x400FC104 0x00000003; # Setup Clock Divider
mww 0x400FC10C 0x00000000; # Select Clock Source for PLL0
mww 0x400FC084 0x000300c7; # /* configure PLL0 */
mww 0x400FC08C 0xAA; #FEED_seq_0
mww 0x400FC08C 0x55; #FEED_seq_1
mww 0x400FC080 0x00000001; # /* PLL0 Enable
*/
mww 0x400FC08C 0xAA; #FEED_seq_0
mww 0x400FC08C 0x55; #FEED_seq_1
#while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0
*/
sleep 50
mdw 0x400FC088; #For debugging purposes
mww 0x400FC080 0x00000003; # /* PLL0 Enable & Connect
*/
mww 0x400FC08C 0xAA; #FEED_seq_0
mww 0x400FC08C 0x55; #FEED_seq_1
#while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for
PLLC0_STAT & PLLE0_STAT */
sleep 50
mdw 0x400FC088; #For debugging purposes
mww 0x400FC1C8 0x00000000; # /* Clock Output Configuration */
mww 0x400FC000 0x0000503A; # /* flash accelerator to safe mode
<-- is this really needed */
echo "Done initializing PLL"
On 22 May 2012 01:30, Akos Vandra <[email protected]> wrote:
> Hi!
>
> I am using a kt-link interface with the new mpsse drivers.
> I am trying to write a programming script for the lpc17xx devices
> (which I will be more than happy to share if ready), that basically
> does this:
>
> (1. reset the target)
> 2. halt the target
> 3. configure pll for max cpu frequency (100MHz)
> 4. write a file to flash.
>
> However as soon as I start to mendle with the PLL registers, openocd
> loses connection. IMHO it shouldn't as the CPU can handle disabling
> the PLL mid-run, and from the uC code it works.
>
> What I do, is I write 0 to the PLL0CON register bit, which should
> route the non-plled clock source to the CPU frequency. After that I
> would disable the pll entirely before setting it up with the new
> values, but the script never reaches that point.
>
> My script basically calls this function:
>
> proc program { } {
>
> adapter_khz 100
>
> # jtag_reset 0 1
> reset halt
> # halt 0
> # jtag_reset 0 0
> # wait_halt
>
> mdw 0x400FC084
> mdw 0x400FC088
>
> echo bypassing
> #Bypass PLL if in use
> mww 0x400FC080 0x00000001; # /* PLL0 Disconnect
> */
> mww 0x400FC08C 0xAA; #FEED_seq_0
> mww 0x400FC08C 0x55; #FEED_seq_1
> echo X
> sleep 1000
> echo Y
> mww 0x400FC080 0x00000000; # /* PLL0 Disable */
> mww 0x400FC08C 0xAA; #FEED_seq_0
> mww 0x400FC08C 0x55; #FEED_seq_1
> echo done
>
>
> (...........)
> akos@FM12BQ:~/Downloads/_openocd/openocd$ src/openocd -f openocd.cfg
> -s tcl -c init -c program
> Open On-Chip Debugger 0.6.0-dev-00557-g61d38c5-dirty (2012-05-21-22:38)
> Licensed under GNU GPL v2
> For bug reports, read
> http://openocd.sourceforge.net/doc/doxygen/bugs.html
> Info : only one transport option; autoselect 'jtag'
> adapter_nsrst_delay: 200
> 10 kHz
> 666 kHz
> Info : clock speed 666 kHz
> Info : JTAG tap: lpc1768.cpu tap/device found: 0x4ba00477 (mfg: 0x23b,
> part: 0xba00, ver: 0x4)
> Info : lpc1768.cpu: hardware has 6 breakpoints, 4 watchpoints
> 100 kHz
> Info : JTAG tap: lpc1768.cpu tap/device found: 0x4ba00477 (mfg: 0x23b,
> part: 0xba00, ver: 0x4)
> Warn : Only resetting the Cortex-M3 core, use a reset-init event
> handler to reset any peripherals
> target state: halted
> target halted due to debug-request, current mode: Thread
> xPSR: 0x01000000 pc: 0x1fff0080 msp: 0x10001ffc
> 0x400fc084: 0006010e
> 0x400fc088: 0706010e
> bypassing
> Feed
> Polling target failed, GDB will be halted. Polling again in 100ms
> X
> Polling target failed, GDB will be halted. Polling again in 300ms
> Polling target failed, GDB will be halted. Polling again in 700ms
> Polling target failed, GDB will be halted. Polling again in 1500ms
> Polling target failed, GDB will be halted. Polling again in 3100ms
> Polling target failed, GDB will be halted. Polling again in 6300ms
> Polling target failed, GDB will be halted. Polling again in 6300ms
> Y
> Warn : Block read error address 0x400fc084
> Runtime Error: openocd.cfg:26:
> in procedure 'program'
> in procedure 'mdw' called at file "openocd.cfg", line 26
> akos@FM12BQ:~/Downloads/_openocd/openocd$
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