On Thu, Jun 14, 2012 at 12:02 AM, jim norris <[email protected]> wrote: > Frank, > > Are you using he Origen board? > > Jim
No. I'm using the soon to be released "cotton candy", but that feature the same Exynos 4210 as the Origenboard, so the target port should be applicable to the Origenboard as well. "Exynos" may be a bit ambiguos nowadays, so I should probably call the port Exynos4. A minor sematic correction to my first question: I meant to say that I have problems with the CORE_HALTED bit not being set after writing to DSCR with DSCR[HALT_DBG_MODE] asserted, which is the timeout cause. It's not the test/read-op that causes the timeout :-) Cheers, Frank ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
