On Wed, Jun 13, 2012 at 11:20:00PM +0200, Frank Svendsboe wrote: > Hi > > I'm trying to port OpenOCD to the Exynos (2 x Cortex A9), but > experience some issues: > > 1) Halting the CPUs via the CP14 interface don't work > properly/stable. I very often get a timeout after reading the HALTED > bit in the DSCR (see cortex_a8_halt in src/target/cortex_a.c.). > > 2) Given there's no quick fix for 1), i'd like to try to halt using > the CoreSight Debug Logic processor. I've got the address for it from > the DAP ROM table, so it's probably possible, but I wonder if anyone > else is working on CoreSight support in OpenOCD. Also, from reading > the arch. reference manual, it seems the opcode/command interface is > deprecated? >
Here's a short status update reg. the problems above: Using the correct reset_config setting and using a slow adapter clk solved the problem listed above. Now I can halt, inspect registers on both cpus, and resume.. but I have another problem when stepping. Using 'ni' from gdb leads to => Error: JTAG-DP STICKY ERROR Warn: Block read error address 0x0 ... However, after the noisy output above it manages to fetch and run the next instruction (and a "x/5i $pc" shows sane output). Now, 1) Anyone else seen this JTAG-DP STICKY ERROR problem even when running very slow adapter speed (15kHZ) 2) Any clue on why the Flyswatter2 adaptive clocking don't seemingly work (tried jtag_rclk 1000/100/10). If I use "jtag_rclk 10" the DAP it not recognized. Cheers, Frank ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
