> -----Original Message-----
> From: Philippe Mathieu-Daudé <phi...@linaro.org>
> Sent: Monday, February 5, 2024 9:20 PM
> To: Jamin Lin <jamin_...@aspeedtech.com>; Cédric Le Goater <c...@kaod.org>;
> Peter Maydell <peter.mayd...@linaro.org>; Andrew Jeffery
> <and...@codeconstruct.com.au>; Joel Stanley <j...@jms.id.au>; open
> list:ASPEED BMCs <qemu-...@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_...@aspeedtech.com>
> Subject: Re: [PATCH v0 2/2] aspeed: fix hardcode boot address 0
>
> Hi Jamin,
>
> On 5/2/24 10:14, Jamin Lin via wrote:
> > In the previous design of QEMU model for ASPEED SOCs, it set the boot
> > address at 0 which was the hardcode setting for ast10x0, ast2600,
> > ast2500 and ast2400.
> >
> > According to the design of ast2700, it has bootmcu which is used for
> > executing SPL and initialize DRAM,
>
> Out of curiosity, what architecture is this MCU?
MCU is riscv-ibex and its architecture is riscv-32.
>
> > then, CPUs(cortex-a35)
> > execute u-boot, kernel and rofs. QEMU will only support
> > CPU(coretax-a35) parts and the boot address is "0x400000000" for ast2700.
>
> OK, but I don't get how you get from here ...
>
Our design make MCU execute SPL and copy u-boot image from SPI to DRAM at
address 0x400000000 at SPL boot stage.
However, QEMU will only support to emulate CPU sides (coretex-a35) for ast2700,
that was why we want to change the boot address at 0x400000000
And use the following start command by QEMU.
./qemu-system-aarch64 -M ast2750-evb -nographic -m 8G \
-device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on \
-device loader,addr=$((0x400000000 +
${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb,force-raw=on \
---
---
By the way, I will send a new patch series to support ast2700 in two weeks and
We set memory map for ast2700 as following.
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = 0x400000000,
[ASPEED_DEV_SRAM] = 0x10000000,
Jamin
> > Therefore, fixed hardcode boot address 0.
>
> ... to here.
>
> > Signed-off-by: Troy Lee <troy_...@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
> > ---
> > hw/arm/aspeed.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index
> > 218b81298e..82a92e8142 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -289,12 +289,14 @@ static void
> aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
> > uint64_t rom_size)
> > {
> > AspeedSoCState *soc = bmc->soc;
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
> >
> > memory_region_init_rom(&bmc->boot_rom, NULL,
> "aspeed.boot_rom", rom_size,
> > &error_abort);
> > memory_region_add_subregion_overlap(&soc->spi_boot_container,
> 0,
> > &bmc->boot_rom, 1);
> > - write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size,
> &error_abort);
> > + write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
> > + rom_size, &error_abort);
>
> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
>
> > }
> >
> > void aspeed_board_init_flashes(AspeedSMCState *s, const char
> > *flashtype,
