On 3/4/24 21:03, Jinjie Ruan via wrote:
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan<ruanjin...@huawei.com>
---
v6:
- Verify that HCR_EL2.VF is set before checking VFNMI.
v4；
- Also handle VNMI.
v3:
- CPU_INTERRUPT_NMI do not set FIQ, so remove it.
- With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set.
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
