On Mon, Jun 19, 2023 at 4:23 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The microblaze architecture does not reorder instructions.
> While there is an MBAR wait-for-data-access instruction,
> this concerns synchronizing with DMA.
>
> This should have been defined when enabling MTTCG.
Reviewed-by: Edgar E. Iglesias <ed...@zeroasic.com>
There might be MicroBlaze systems that allow reordering of load vs store
streams but it doesn't seem to be documented and I'm not 100% certain so
this change LGTM!
Thanks,
Edgar
>
> Cc: Alistair Francis <alistair.fran...@wdc.com>
> Cc: Edgar E. Iglesias <edgar.igles...@gmail.com>
> Fixes: d449561b130 ("configure: microblaze: Enable mttcg")
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/microblaze/cpu.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 88324d0bc1..b474abcc2a 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -24,6 +24,9 @@
> #include "exec/cpu-defs.h"
> #include "qemu/cpu-float.h"
>
> +/* MicroBlaze is always in-order. */
> +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
> +
> typedef struct CPUArchState CPUMBState;
> #if !defined(CONFIG_USER_ONLY)
> #include "mmu.h"
> --
> 2.34.1
>
>
