[casper] Fwd: MIRIAD FILE // IBOB CORRELATOR
I had problems with add image, then copy the text: rolando@rolando-MS-7815:~/ibob/poco011$ poco_rx_i8_c256.py i8_c256.config Parsing config file i8_c256.config...OK Listening on port 7 Expecting integration sizes of 18432 vectors, or 73728 bytes C2M Parameters: N Antennas: 8 Bandwidth: 0.20 GHz SDF: 0.000781 GHz Int Time: 0.41 s Array location: ['38:25:59.24', '-79:51:02.1'] Recording Bandpass to file... Traceback (most recent call last): File /usr/local/bin/poco_rx_i8_c256.py, line 408, in module udp_rx.set_bandpass() File /usr/local/bin/poco_rx_i8_c256.py, line 124, in set_bandpass bps.shape=(self.n_ants,self.n_chans) ValueError: total size of new array must be unchanged rolando@rolando-MS-7815:~/ibob/poco011$ -- Forwarded message -- From: Rolando Paz flx...@gmail.com Date: 2014-03-21 1:28 GMT-06:00 Subject: MIRIAD FILE // IBOB CORRELATOR To: casper@lists.berkeley.edu casper@lists.berkeley.edu Hi everyone ... Regarding my problem with python and IBOB was the use of a wrong conf file :-) Now I found a new problem. Attached image. I also think that now I must enter the correct data, inside scripts, to obtain the correct file MIRIAD. I hope someone can guide me. Best Regards Rolando Paz
Re: [casper] KatADC vs ASIAA ADC
Hi Dan Thanks for your input. For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall order, we could settle for 1024. I am hoping to double the number of channels for halving the BW. For eg. BW NumChannels 8002048 4004096 2008192 I see why you are suggesting the ASIAA dual adc card for the 800 MHz mode. But I would prefer if we could use the same ADC for all modes. If I were to use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use all 8 parallel streams of the ADC for PFB and FFT then I satisfy that mode. For the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but terminate 4 outputs of the 8 parallel streams from the ADC, am I not effectively sampling at 800 MHz? Can a similar argument not be applied for 400 MHz sampling? What are the downsides to taking this approach? Am I missing something obvious? Cheers, Gopal On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer d...@ssl.berkeley.eduwrote: hi gopal, how many spectral channels do you need? for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps, and get four signal inputs per roach2, and clock the fgpa at 250 MHz. . for 400 MHz bandwidth, i suggest you use a pair of adc16 boards in quad input mode (sample at 960 Msps, four inputs per board), so you can get 8 signal inputs per roach2. fpga clock of 240 MHz. we might have a design for this you can use if you'd like. for 200 MHz bandwidth, i suggest you use a pair of adc16 boards in octal input mode (sample at 480 Msps, eight inputs per board), so you can get 16 signal inputs per roach2. fpga clock of 240 MHz. best wishes, dan On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan go...@astro.umass.eduwrote: Hello Casperites I'm looking for advice. We are at the point of launching into a wideband spectrometer project for building ROACH-2 based spectrometers to handle 32 independent front-end inputs. This is a conventional spectrometer (no cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are also interested in modes of bandwidth 200 and 400 MHz. I should note that legacy IF processors with band-limiting filters for the above BWs already exist, and we are building our spectrometer to these bandwidths. I am debating between the KatADC board and the wideband ASIAA 5GSPS ADC based boards. I ran some preliminary Simulink designs with the KatADC boards, and I run into timing issues when I use ADC sampling rate 1200 MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into one ROACH-2 if possible. Has anyone run the KatADC close to its maximum sampling rate with the ROACH-2s? Are plan-ahead and other more advanced techniques needed for this? Alternatively, we could use the ASIAA ADC board, which has a divided-by-8 for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at nominal values might be easier with the ASIAA board, especially when we are only interested in relatively low sample clocks to 1.6 GHz. We are considering the 8-bit DMUX 1:1 version of the ASIAA board. Any pointers/advice/suggestions in choosing an appropriate ADC board is appreciated! Thanks Gopal -- Gopal Narayanan Ph #: (413) 545 0925 Department of Astronomy e-mail: go...@astro.umass.edu University of Massachusetts Amherst MA 01003 -- Gopal Narayanan Ph #: (413) 545 0925 Department of Astronomy e-mail: go...@astro.umass.edu University of Massachusetts Amherst MA 01003
Re: [casper] KatADC vs ASIAA ADC
John We do have switchable analog filters that define the 200, 400 and 800 MHz bandpasses in our IF processors. So decimation in sample domain should still work. Yes, that's true. In our case we want to avoid the complexity of switching in various bandpass filters for the narrowband case. So your point about the relatively slow 200 MHz FPGA speed is that it may make more sense to keep the sampling clock a little higher (say 2GHz) so that FPGA is at a higher clock rate (250 MHz), and use digital filtering (in addition to the defined analog band) to define the bandwidths? Yes, I think that without tweaking the clock management that you can't run the FPGA slow enough for 200 MHz /16, and as you say, simply decimating the output of the ADC ought to work given a reasonable clock rate, like 800 MHz. A related question for you. For VEGAS, I thought you were using ADC1x3000-8. Can it go to 3.2 GS/s? Or are you using the ASIAA ADC? We switched mid-stream to the ASIAA ADC. It's faster, cheaper, and has better performance. John Thanks! Gopal On Fri, Mar 21, 2014 at 1:30 PM, John Ford jf...@nrao.edu wrote: Hi Dan Thanks for your input. For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall order, we could settle for 1024. This isn't a problem using roach-2 I am hoping to double the number of channels for halving the BW. For eg. BW NumChannels 8002048 4004096 2008192 You can use just one ADC for all of your modes, I think. I see why you are suggesting the ASIAA dual adc card for the 800 MHz mode. But I would prefer if we could use the same ADC for all modes. If I were to use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use all 8 parallel streams of the ADC for PFB and FFT then I satisfy that mode. For the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but terminate 4 outputs of the 8 parallel streams from the ADC, am I not effectively sampling at 800 MHz? Can a similar argument not be applied for 400 MHz sampling? What are the downsides to taking this approach? Am I missing something obvious? We're looking into doing this, except we may sample faster (at either 1.6 GS/s or 3.2 GS/s) and digitally filter down to the other rates to avoid having more analog filters in the system. You will likely have trouble trying to just scale the sample clock down, because at the 200 MHz point, your FPGA will be clocking too slowly. Your idea of decimating the sample input will probably work well, but you will have to have analog filters to define the bandpass. John Cheers, Gopal On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer d...@ssl.berkeley.eduwrote: hi gopal, how many spectral channels do you need? for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps, and get four signal inputs per roach2, and clock the fgpa at 250 MHz. . for 400 MHz bandwidth, i suggest you use a pair of adc16 boards in quad input mode (sample at 960 Msps, four inputs per board), so you can get 8 signal inputs per roach2. fpga clock of 240 MHz. we might have a design for this you can use if you'd like. for 200 MHz bandwidth, i suggest you use a pair of adc16 boards in octal input mode (sample at 480 Msps, eight inputs per board), so you can get 16 signal inputs per roach2. fpga clock of 240 MHz. best wishes, dan On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan go...@astro.umass.eduwrote: Hello Casperites I'm looking for advice. We are at the point of launching into a wideband spectrometer project for building ROACH-2 based spectrometers to handle 32 independent front-end inputs. This is a conventional spectrometer (no cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are also interested in modes of bandwidth 200 and 400 MHz. I should note that legacy IF processors with band-limiting filters for the above BWs already exist, and we are building our spectrometer to these bandwidths. I am debating between the KatADC board and the wideband ASIAA 5GSPS ADC based boards. I ran some preliminary Simulink designs with the KatADC boards, and I run into timing issues when I use ADC sampling rate 1200 MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into one ROACH-2 if possible. Has anyone run the KatADC close to its maximum sampling rate with the ROACH-2s? Are plan-ahead and other more advanced techniques needed for this? Alternatively, we could use the ASIAA ADC board, which has a divided-by-8 for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at nominal values might be easier with the ASIAA board, especially when we are only interested in relatively low sample clocks to 1.6 GHz. We are considering
Re: [casper] ROACH-2 defaulting to netboot
Hi Richard, Do you have the USB cable connected a terminal program running, where you can watch it boot up? If so, once you hit any key to interrupt the boot, you type: setenv bootcmd run netboot saveenv That should do it. Jason On Fri, 21 Mar 2014, Richard Black wrote: Hi all, I'm having trouble getting our ROACH-2 board to select netboot as the default boot option. My perusing of the wiki has yield few results. Does anybody know how to do this? Thanks, Richard Black
Re: [casper] KatADC vs ASIAA ADC
Hi John If you can sample 800 MHz bandwidth, then can't you use a digitial bandpass filter to get to the lower bandwidths? Gerry On 3/21/2014 11:43 AM, John Ford wrote: John We do have switchable analog filters that define the 200, 400 and 800 MHz bandpasses in our IF processors. So decimation in sample domain should still work. Yes, that's true. In our case we want to avoid the complexity of switching in various bandpass filters for the narrowband case. So your point about the relatively slow 200 MHz FPGA speed is that it may make more sense to keep the sampling clock a little higher (say 2GHz) so that FPGA is at a higher clock rate (250 MHz), and use digital filtering (in addition to the defined analog band) to define the bandwidths? Yes, I think that without tweaking the clock management that you can't run the FPGA slow enough for 200 MHz /16, and as you say, simply decimating the output of the ADC ought to work given a reasonable clock rate, like 800 MHz. A related question for you. For VEGAS, I thought you were using ADC1x3000-8. Can it go to 3.2 GS/s? Or are you using the ASIAA ADC? We switched mid-stream to the ASIAA ADC. It's faster, cheaper, and has better performance. John Thanks! Gopal On Fri, Mar 21, 2014 at 1:30 PM, John Ford jf...@nrao.edu wrote: Hi Dan Thanks for your input. For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall order, we could settle for 1024. This isn't a problem using roach-2 I am hoping to double the number of channels for halving the BW. For eg. BW NumChannels 8002048 4004096 2008192 You can use just one ADC for all of your modes, I think. I see why you are suggesting the ASIAA dual adc card for the 800 MHz mode. But I would prefer if we could use the same ADC for all modes. If I were to use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use all 8 parallel streams of the ADC for PFB and FFT then I satisfy that mode. For the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but terminate 4 outputs of the 8 parallel streams from the ADC, am I not effectively sampling at 800 MHz? Can a similar argument not be applied for 400 MHz sampling? What are the downsides to taking this approach? Am I missing something obvious? We're looking into doing this, except we may sample faster (at either 1.6 GS/s or 3.2 GS/s) and digitally filter down to the other rates to avoid having more analog filters in the system. You will likely have trouble trying to just scale the sample clock down, because at the 200 MHz point, your FPGA will be clocking too slowly. Your idea of decimating the sample input will probably work well, but you will have to have analog filters to define the bandpass. John Cheers, Gopal On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer d...@ssl.berkeley.eduwrote: hi gopal, how many spectral channels do you need? for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps, and get four signal inputs per roach2, and clock the fgpa at 250 MHz. . for 400 MHz bandwidth, i suggest you use a pair of adc16 boards in quad input mode (sample at 960 Msps, four inputs per board), so you can get 8 signal inputs per roach2. fpga clock of 240 MHz. we might have a design for this you can use if you'd like. for 200 MHz bandwidth, i suggest you use a pair of adc16 boards in octal input mode (sample at 480 Msps, eight inputs per board), so you can get 16 signal inputs per roach2. fpga clock of 240 MHz. best wishes, dan On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan go...@astro.umass.eduwrote: Hello Casperites I'm looking for advice. We are at the point of launching into a wideband spectrometer project for building ROACH-2 based spectrometers to handle 32 independent front-end inputs. This is a conventional spectrometer (no cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are also interested in modes of bandwidth 200 and 400 MHz. I should note that legacy IF processors with band-limiting filters for the above BWs already exist, and we are building our spectrometer to these bandwidths. I am debating between the KatADC board and the wideband ASIAA 5GSPS ADC based boards. I ran some preliminary Simulink designs with the KatADC boards, and I run into timing issues when I use ADC sampling rate 1200 MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into one ROACH-2 if possible. Has anyone run the KatADC close to its maximum sampling rate with the ROACH-2s? Are plan-ahead and other more advanced techniques needed for this? Alternatively, we could use the ASIAA ADC board, which has a divided-by-8 for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at nominal values might be easier with the ASIAA board, especially when we are only interested in relatively low sample clocks to 1.6 GHz. We are
