[casper] FPGA Vendor to consider

[Jonathan Weintroub]

For those of CASPERites, especially those in the US, looking to purchase FPGAs, 
you might share my frustration that the price quoted by the Xilinx franchised 
distributors in the US (Avnet and Digikey) doesn’t seem to decay with time or 
quantity, nor it is easy in my experience to negotiate better pricing.

With some trepidation around August last year we purchased a dozen V6-SX475T in 
-2 speed grade from a non-franchised distributer, to which I think I was 
referred by the Octopart website.   They quoted attractive pricing for -2  
parts (quite a bit less than the franchised price for -1) and a long lead time 
(22 weeks).  I did some due diligence checking a few references etc, and bit 
the bullet.   They substantially beat the lead time delivering in about 3 
weeks, and now that the parts are assembled onto ROACH2s as best we can tell 
they are functional. 

So with the caveat that your mileage may vary here is a suggested vendor to 
consider:

EarthTron, LLC
210 West Road, Unit 6
Portsmouth, NH 03801
Toll-free: 800-322-2130

Jason Miles
Senior OEM Sales
main603-433-2007 Ext 126
direct  603-766-6310
fax 603-433-2007
email   jason.mi...@earthtron.com
google talk jason.mi...@earthtron.com   

Jason says the parts the supplied were sourced from Xilinx, exactly the meaning 
of the term “franchised distributer” is, and the pricing policy remains a bit 
of a mystery to me.

Cheers,

Jonathan

Re: [casper] fft_biplex_real_2x

[Ryan Monroe]

I don't use the stock CASPER FFTs anymore, but I'm pretty sure that 
there's no way to use them for anything less than {2 complex inputs 
--OR-- 4 real inputs}.  If you want less, you can drive an input with a 
constant '0', but resource-wise, they're the same.  This is because of 
algorithmic limitations; there is a resource efficiency you gain by 
doing two complex FFTs at once.


This is a time for a streaming Xilinx FFT.

--Ryan

On 01/19/2016 09:49 PM, James Smith wrote:

Hi Rolando,

I can't recall that it does, off the top of my head, but the Casper 
one can be set up to use just one input. This is what I've done in the 
past, I think.


Regards,
James


On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz > wrote:


Hi James and Andrew

Thank for yours advices.

I'm trying to recompile the design of Peter McMahon:
https://casper.berkeley.edu/wiki/Parspec

I'm using these libraries:

https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20

and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS,
Matlab R2007b,
ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC.

With this configuration, I can not compile this new design.

I'll try with Xilinx FFT...
Is there a Xilinx block version for the PFB too?

Thank you.



2016-01-19 23:23 GMT-06:00 Andrew Martens >:

Hi Rolando

You may want to look at the Xilinx FFT for your use case. The
CASPER FFT is optimised so that minimal resources are used
when processing high bandwidths (either many inputs, or inputs
captured at high sample rates). In this case you may find that
the Xilinx FFT actually uses fewer resources.

Regards
Andrew

On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz
> wrote:

Hi

Is there any other FFT block that I can use with ADC4x250-8?

https://casper.berkeley.edu/wiki/ADC4x250-8

I am using the "fft_biplex_real_2x" block, however I need
only one input of the four that this block has. I placed
at zero the others three inputs.

I need more FPGA resources from IBOB, and I think using
another FFT block may be one solution.

Best Regards

RP

Re: [casper] fft_biplex_real_2x

[Rolando Paz]

Hi

In the attached picture you can see the fft xilinx blocks I found.

Which one should I use?
How should I set this block?


2016-01-20 3:06 GMT-06:00 Ryan Monroe :

> I don't use the stock CASPER FFTs anymore, but I'm pretty sure that
> there's no way to use them for anything less than {2 complex inputs --OR--
> 4 real inputs}.  If you want less, you can drive an input with a constant
> '0', but resource-wise, they're the same.  This is because of algorithmic
> limitations; there is a resource efficiency you gain by doing two complex
> FFTs at once.
>
> This is a time for a streaming Xilinx FFT.
>
> --Ryan
>
>
> On 01/19/2016 09:49 PM, James Smith wrote:
>
> Hi Rolando,
>
> I can't recall that it does, off the top of my head, but the Casper one
> can be set up to use just one input. This is what I've done in the past, I
> think.
>
> Regards,
> James
>
>
> On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz  wrote:
>
>> Hi James and Andrew
>>
>> Thank for yours advices.
>>
>> I'm trying to recompile the design of Peter McMahon:
>> https://casper.berkeley.edu/wiki/Parspec
>>
>> I'm using these libraries:
>>
>> https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20
>>
>> and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS, Matlab
>> R2007b,
>> ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC.
>>
>> With this configuration, I can not compile this new design.
>>
>> I'll try with Xilinx FFT...
>> Is there a Xilinx block version for the PFB too?
>>
>> Thank you.
>>
>>
>>
>> 2016-01-19 23:23 GMT-06:00 Andrew Martens < 
>> and...@ska.ac.za>:
>>
>>> Hi Rolando
>>>
>>> You may want to look at the Xilinx FFT for your use case. The CASPER FFT
>>> is optimised so that minimal resources are used when processing high
>>> bandwidths (either many inputs, or inputs captured at high sample rates).
>>> In this case you may find that the Xilinx FFT actually uses fewer
>>> resources.
>>>
>>> Regards
>>> Andrew
>>>
>>> On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz  wrote:
>>>
 Hi

 Is there any other FFT block that I can use with ADC4x250-8?

 https://casper.berkeley.edu/wiki/ADC4x250-8

 I am using the "fft_biplex_real_2x" block, however I need only one
 input of the four that this block has. I placed at zero the others three
 inputs.

 I need more FPGA resources from IBOB, and I think using another FFT
 block may be one solution.

 Best Regards

 RP

>>>
>>>
>>
>
>

Re: [casper] fft_biplex_real_2x

[James Smith]

Hi Rolando,

I'll refer you to Xilinx Sysgen's reference documents. You should be able
to get them from their website. They contain all the info you need about
those blocks.

The different FFT versions will depend on your board - I'm not familiar
with the iBOB, so I'm not sure which FPGA it has on it, but the older FPGAs
don't support the newer FFT designs.

You can set it up depending on your needs - speed or space. I'd suggest
doing a few simulations to get a feel for how the various FFTs work. These
don't take too long and will give you a good feel for what's available.

Regards,
James


On Wed, Jan 20, 2016 at 3:40 PM, Rolando Paz  wrote:

> Hi
>
> In the attached picture you can see the fft xilinx blocks I found.
>
> Which one should I use?
> How should I set this block?
>
>
> 2016-01-20 3:06 GMT-06:00 Ryan Monroe :
>
>> I don't use the stock CASPER FFTs anymore, but I'm pretty sure that
>> there's no way to use them for anything less than {2 complex inputs --OR--
>> 4 real inputs}.  If you want less, you can drive an input with a constant
>> '0', but resource-wise, they're the same.  This is because of algorithmic
>> limitations; there is a resource efficiency you gain by doing two complex
>> FFTs at once.
>>
>> This is a time for a streaming Xilinx FFT.
>>
>> --Ryan
>>
>>
>> On 01/19/2016 09:49 PM, James Smith wrote:
>>
>> Hi Rolando,
>>
>> I can't recall that it does, off the top of my head, but the Casper one
>> can be set up to use just one input. This is what I've done in the past, I
>> think.
>>
>> Regards,
>> James
>>
>>
>> On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz  wrote:
>>
>>> Hi James and Andrew
>>>
>>> Thank for yours advices.
>>>
>>> I'm trying to recompile the design of Peter McMahon:
>>> https://casper.berkeley.edu/wiki/Parspec
>>>
>>> I'm using these libraries:
>>>
>>> https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20
>>>
>>> and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS, Matlab
>>> R2007b,
>>> ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC.
>>>
>>> With this configuration, I can not compile this new design.
>>>
>>> I'll try with Xilinx FFT...
>>> Is there a Xilinx block version for the PFB too?
>>>
>>> Thank you.
>>>
>>>
>>>
>>> 2016-01-19 23:23 GMT-06:00 Andrew Martens < 
>>> and...@ska.ac.za>:
>>>
 Hi Rolando

 You may want to look at the Xilinx FFT for your use case. The CASPER
 FFT is optimised so that minimal resources are used when processing high
 bandwidths (either many inputs, or inputs captured at high sample rates).
 In this case you may find that the Xilinx FFT actually uses fewer
 resources.

 Regards
 Andrew

 On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz  wrote:

> Hi
>
> Is there any other FFT block that I can use with ADC4x250-8?
>
> https://casper.berkeley.edu/wiki/ADC4x250-8
>
> I am using the "fft_biplex_real_2x" block, however I need only one
> input of the four that this block has. I placed at zero the others three
> inputs.
>
> I need more FPGA resources from IBOB, and I think using another FFT
> block may be one solution.
>
> Best Regards
>
> RP
>


>>>
>>
>>
>