Re: [casper] Unable to Load Firmware Image onto SKARAB

[Adam Isaacson]

Hi Jonathan and Mark,

Thanks for the feedback. The documentation is a work in progress, so
feedback is important.

I will certainly add a How To on configuring the SKARAB via the JTAG and we
are/will be working on a user manual for casperfpga.

The schematics are part of the "Peralex Documentation" link I sent to you
earlier today. Check the link, it is there.

Here are the relevant ones explained (for general CASPER community use):

1) How to install Vivado on Ubuntu 14.04LTS (https://drive.google.com/
drive/folders/0B2dCFqGD5y-8YTNGT0wzZTFXU1E?usp=sharing). I am currently
using Vivado 2016.2 and I suggest using the same. The How To document
explains how to install: 2014.3.1, 2015.4 and 2016.2. NB: Rule of thumb I
follow, if you are working with Vivado 2016 then use the corresponding year
for the Matlab version i.e. R2016a or R2016b. If you don't then there will
be issues with compatibility regarding the system generator tools. It is a
step by step how to, so should be detailed enough to install.

2) How to install Matlab on Ubuntu 14.04LTS (https://drive.google.com/
drive/folders/0B2dCFqGD5y-8anluUTg1ZjZxbWc?usp=sharing). I am currently
using Matlab R2016b and I suggest using the same. The How To document
explains how to install: Matlab R2012b, R2015b and R2016b. I have only ever
used R2015b and R2016b with the JASPER toolflow - R2012b has been used with
the old CASPER toolflow and with Xilinx ISE 14.7. This How To may help
Arash with the issue regarding the LIBSTDC files.

3) How to use the new JASPER toolflow using Matlab/Python or just from
Python (https://docs.google.com/document/d/131VGftG8QoCVqnm5unFcj0pplnPoI
17urIgvb-qymu4/edit?usp=sharing). This document will explain how to run the
commands in order to generate a fpg file either using matlab with python or
just directly from python. It explains the arguments for the exec_flow
command. This is a very useful document and should be read.

4) The JASPER toolflow mlib_devel directory explained (
https://docs.google.com/document/d/1L0j6vihbT2DsT45SrWc58J2htheJD
W4cpQxUw-wlf0E/edit?usp=sharing). This is what Jack Hickish sent to me at
the beginning of the year explaining the new mlib_devel directory
structure. This is useful for Mark and anyone else who is new to CASPER.

This will be placed on GitHub before the CASPER 2017 conference.

I hope this answers your questions.

Kind regards,

Adam





On Thu, Jun 15, 2017 at 12:45 AM, Jonathan Weintroub <
jweintr...@cfa.harvard.edu> wrote:

> Hi Adam,
>
> Ok thanks.  I found a Xilinx Platform USB pod in anticipation of this need
> before leaving the office.  I still need to locate the fly lead cables.
> For this reason alone this needs to wait till tomorrow.  It's also very
> late for you so I feel badly keeping you up.
>
> The package of documents your group assembled and passed on to us is very
> detailed and impressive, and we really appreciate it!
>
> We were discussing today that somehow the most basic procedures need to be
> more tightly packaged and perhaps the board should ship with a set of the
> most needed accessories--a few loop back cables perhaps, maybe even a JTAG
> tickler or similar, maybe a F/O module or twi, and a large clear photo of
> the unit showing what connector and part is where, etc.  Just to make it
> absolutely clear to the new user, especially if not a CASPER insider.This
> especially if it is hoped to market the SKARAB to industry etc
> internationally and more widely.
>
> The package supplied with the typical Xilinx evaluation board is a great
> model, though probably more than can be managed practically speaking.
>
> You mentioned in your response the schematics.  Have full schematics of
> SKARAB been released?  I must have missed them in the package please
> confirm.
>
> Thanks again.
>
> Jonathan
>
> On Wed, Jun 14, 2017 at 6:26 PM Adam Isaacson  wrote:
>
>> Hi Jonathan and Mark,
>>
>>
>> Yes, JTAG is the way. Okay, I have done this before. This is what needs
>> to be done and I am going via memory here - will confirm when I am in the
>> office tomorrow:
>>
>> 1) Remove the SKARAB lid
>> 2) This is TBC, but you will need to short the jumper on P9 (schematic
>> page 42), which will add the Virtex 7 and reconfig device to the JTAG
>> chain. I know I need to do this when I run the Vivado ILA.
>> 3)  The JTAG connector is ref des JP3, which is a 20 pin header. You will
>> need to use the Xilinx USB Platform Programmer Cable to connect to the 20
>> pin header using the fly leads that come with the Xilinx USB Platform
>> Programmer Cable. NB: Remember to install the USB drivers as specified in
>> the Vivado install How To.
>> 4) Open Vivado and open the Hardware Manager. First, auto connect and
>> make sure the FPGA can be detected. Then add the flash device. I used the
>> "mt28gu01gaax1e-bps-x16" device together with the *.MCS files stored in
>> the repo. You just need to configure the multi-boot image to gain access to
>> the board via the 1GbE 

Re: [casper] Unable to Load Firmware Image onto SKARAB

[Jonathan Weintroub]

Hi Adam,

Ok thanks.  I found a Xilinx Platform USB pod in anticipation of this need
before leaving the office.  I still need to locate the fly lead cables.
For this reason alone this needs to wait till tomorrow.  It's also very
late for you so I feel badly keeping you up.

The package of documents your group assembled and passed on to us is very
detailed and impressive, and we really appreciate it!

We were discussing today that somehow the most basic procedures need to be
more tightly packaged and perhaps the board should ship with a set of the
most needed accessories--a few loop back cables perhaps, maybe even a JTAG
tickler or similar, maybe a F/O module or twi, and a large clear photo of
the unit showing what connector and part is where, etc.  Just to make it
absolutely clear to the new user, especially if not a CASPER insider.This
especially if it is hoped to market the SKARAB to industry etc
internationally and more widely.

The package supplied with the typical Xilinx evaluation board is a great
model, though probably more than can be managed practically speaking.

You mentioned in your response the schematics.  Have full schematics of
SKARAB been released?  I must have missed them in the package please
confirm.

Thanks again.

Jonathan

On Wed, Jun 14, 2017 at 6:26 PM Adam Isaacson  wrote:

> Hi Jonathan and Mark,
>
>
> Yes, JTAG is the way. Okay, I have done this before. This is what needs to
> be done and I am going via memory here - will confirm when I am in the
> office tomorrow:
>
> 1) Remove the SKARAB lid
> 2) This is TBC, but you will need to short the jumper on P9 (schematic
> page 42), which will add the Virtex 7 and reconfig device to the JTAG
> chain. I know I need to do this when I run the Vivado ILA.
> 3)  The JTAG connector is ref des JP3, which is a 20 pin header. You will
> need to use the Xilinx USB Platform Programmer Cable to connect to the 20
> pin header using the fly leads that come with the Xilinx USB Platform
> Programmer Cable. NB: Remember to install the USB drivers as specified in
> the Vivado install How To.
> 4) Open Vivado and open the Hardware Manager. First, auto connect and make
> sure the FPGA can be detected. Then add the flash device. I used the "
> mt28gu01gaax1e-bps-x16" device together with the *.MCS files stored in
> the repo. You just need to configure the multi-boot image to gain access to
> the board via the 1GbE interface again. Set the RS pins to [25:24]. You may
> need the *.prm files, which are available in
> https://drive.google.com/drive/folders/0B2dCFqGD5y-8eHlSVlFrUVdPOVE?usp=sharing.
> If you do then let me know and I will add them to the repo.
> 5) Configure the flash, verify and then power off the board and see if the
> 1GbE comes up.
>
> If you are still struggling then I will generate a proper How To document
> tomorrow with graphics etc. I will probably do that anyway.
>
> Good luck!
>
>
>
> On Wed, Jun 14, 2017 at 11:44 PM, Jonathan Weintroub <
> jweintr...@cfa.harvard.edu> wrote:
>
>> Hi Wes and other SKARAB experts,
>>
>> To my understanding our SKARAB is now "bricked" and no longer responds on
>> Ethernet at all. We now need a way to bring it back to life from a straight
>> off the factory floor state.  We surmise this involves JTAG and while there
>> is a tantalizing mention of this protocol in the docs Adam supplied, there
>> are no details.
>>
>> We may need Peralex expert support here.  We are time constrained on this
>> project and need to get rolling.
>>
>> Please advise, thanks!
>>
>> Jonathan Weintroub
>> SAO
>>
>>
>> On Wed, Jun 14, 2017 at 5:11 PM Wesley New  wrote:
>>
>>> Hi Mark,
>>>
>>> Firstly, welcome to the CASPER community.
>>>
>>> The SKARAB has multiple images stored in Flash. These are meant only
>>> used for the initial FPGA image at start up and a fall back image. This is
>>> a Xilinx standard method of configuration. You should be using the
>>> upload_to_ram_and_program function. This function uploads the your compiled
>>> fpg file to the SDRAM and then triggers the Virtex to program itself from
>>> the SDRAM. You will probably have overwritten the boot images. :(
>>>
>>> import casperfpga
>>>
>>> SKARAB_IP = '10.99.45.170'
>>> SKARAB_FPG = 'skarab.fpg'
>>>
>>> # skarab programming
>>> skarab = casperfpga.CasperFpga(SKARAB_IP)
>>> skarab.upload_to_ram_and_program(SKARAB_FPG)
>>>
>>> Does the board come back after waiting some time?
>>>
>>>
>>>
>>>
>>> Wesley New
>>> South African SKA Project
>>> +2721 506 7300 <+27%2021%20506%207300>
>>> www.ska.ac.za
>>>
>>>
>>>
>>> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
>>> mark.per...@cfa.harvard.edu> wrote:
>>>
 Hello,

 After trying to reconfigure the flash memory on the Virtex7 FPGA with a
 new image, I am no longer able to connect to the SKARAB through casperfpga
 using the 1GigE port. When I enter the command fpga =
 casperfpga.SkarabFpga('169.254.128.213'), the following is output.

 

Re: [casper] Unable to Load Firmware Image onto SKARAB

[Adam Isaacson]

Hi Jonathan and Mark,


Yes, JTAG is the way. Okay, I have done this before. This is what needs to
be done and I am going via memory here - will confirm when I am in the
office tomorrow:

1) Remove the SKARAB lid
2) This is TBC, but you will need to short the jumper on P9 (schematic page
42), which will add the Virtex 7 and reconfig device to the JTAG chain. I
know I need to do this when I run the Vivado ILA.
3)  The JTAG connector is ref des JP3, which is a 20 pin header. You will
need to use the Xilinx USB Platform Programmer Cable to connect to the 20
pin header using the fly leads that come with the Xilinx USB Platform
Programmer Cable. NB: Remember to install the USB drivers as specified in
the Vivado install How To.
4) Open Vivado and open the Hardware Manager. First, auto connect and make
sure the FPGA can be detected. Then add the flash device. I used the "
mt28gu01gaax1e-bps-x16" device together with the *.MCS files stored in the
repo. You just need to configure the multi-boot image to gain access to the
board via the 1GbE interface again. Set the RS pins to [25:24]. You may
need the *.prm files, which are available in
https://drive.google.com/drive/folders/0B2dCFqGD5y-8eHlSVlFrUVdPOVE?usp=sharing.
If you do then let me know and I will add them to the repo.
5) Configure the flash, verify and then power off the board and see if the
1GbE comes up.

If you are still struggling then I will generate a proper How To document
tomorrow with graphics etc. I will probably do that anyway.

Good luck!



On Wed, Jun 14, 2017 at 11:44 PM, Jonathan Weintroub <
jweintr...@cfa.harvard.edu> wrote:

> Hi Wes and other SKARAB experts,
>
> To my understanding our SKARAB is now "bricked" and no longer responds on
> Ethernet at all. We now need a way to bring it back to life from a straight
> off the factory floor state.  We surmise this involves JTAG and while there
> is a tantalizing mention of this protocol in the docs Adam supplied, there
> are no details.
>
> We may need Peralex expert support here.  We are time constrained on this
> project and need to get rolling.
>
> Please advise, thanks!
>
> Jonathan Weintroub
> SAO
>
>
> On Wed, Jun 14, 2017 at 5:11 PM Wesley New  wrote:
>
>> Hi Mark,
>>
>> Firstly, welcome to the CASPER community.
>>
>> The SKARAB has multiple images stored in Flash. These are meant only used
>> for the initial FPGA image at start up and a fall back image. This is a
>> Xilinx standard method of configuration. You should be using the
>> upload_to_ram_and_program function. This function uploads the your compiled
>> fpg file to the SDRAM and then triggers the Virtex to program itself from
>> the SDRAM. You will probably have overwritten the boot images. :(
>>
>> import casperfpga
>>
>> SKARAB_IP = '10.99.45.170'
>> SKARAB_FPG = 'skarab.fpg'
>>
>> # skarab programming
>> skarab = casperfpga.CasperFpga(SKARAB_IP)
>> skarab.upload_to_ram_and_program(SKARAB_FPG)
>>
>> Does the board come back after waiting some time?
>>
>>
>>
>>
>> Wesley New
>> South African SKA Project
>> +2721 506 7300 <+27%2021%20506%207300>
>> www.ska.ac.za
>>
>>
>>
>> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
>> mark.per...@cfa.harvard.edu> wrote:
>>
>>> Hello,
>>>
>>> After trying to reconfigure the flash memory on the Virtex7 FPGA with a
>>> new image, I am no longer able to connect to the SKARAB through casperfpga
>>> using the 1GigE port. When I enter the command fpga =
>>> casperfpga.SkarabFpga('169.254.128.213'), the following is output.
>>>
>>> DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
>>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
>>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
>>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
>>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>>> ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not
>>> received.
>>>
>>> My thinking is that the firmware image loaded into the flash is corrupt
>>> and now the 1GigE port is disabled. Are these any other possible ways to
>>> load a firmware image into flash without using the 1GigE port, such as the
>>> USB port or JTAG header? If so, what would be the required procedure to do
>>> so?
>>>
>>> Thanks,
>>>
>>> Mark Peryer
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" group.
>>> To unsubscribe from this group and stop receiving emails from it, send
>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> 

Re: [casper] Unable to Load Firmware Image onto SKARAB

[Jonathan Weintroub]

Hi Wes and other SKARAB experts,

To my understanding our SKARAB is now "bricked" and no longer responds on
Ethernet at all. We now need a way to bring it back to life from a straight
off the factory floor state.  We surmise this involves JTAG and while there
is a tantalizing mention of this protocol in the docs Adam supplied, there
are no details.

We may need Peralex expert support here.  We are time constrained on this
project and need to get rolling.

Please advise, thanks!

Jonathan Weintroub
SAO


On Wed, Jun 14, 2017 at 5:11 PM Wesley New  wrote:

> Hi Mark,
>
> Firstly, welcome to the CASPER community.
>
> The SKARAB has multiple images stored in Flash. These are meant only used
> for the initial FPGA image at start up and a fall back image. This is a
> Xilinx standard method of configuration. You should be using the
> upload_to_ram_and_program function. This function uploads the your compiled
> fpg file to the SDRAM and then triggers the Virtex to program itself from
> the SDRAM. You will probably have overwritten the boot images. :(
>
> import casperfpga
>
> SKARAB_IP = '10.99.45.170'
> SKARAB_FPG = 'skarab.fpg'
>
> # skarab programming
> skarab = casperfpga.CasperFpga(SKARAB_IP)
> skarab.upload_to_ram_and_program(SKARAB_FPG)
>
> Does the board come back after waiting some time?
>
>
>
>
> Wesley New
> South African SKA Project
> +2721 506 7300
> www.ska.ac.za
>
>
>
> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
> mark.per...@cfa.harvard.edu> wrote:
>
>> Hello,
>>
>> After trying to reconfigure the flash memory on the Virtex7 FPGA with a
>> new image, I am no longer able to connect to the SKARAB through casperfpga
>> using the 1GigE port. When I enter the command fpga =
>> casperfpga.SkarabFpga('169.254.128.213'), the following is output.
>>
>> DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not received.
>>
>> My thinking is that the firmware image loaded into the flash is corrupt
>> and now the 1GigE port is disabled. Are these any other possible ways to
>> load a firmware image into flash without using the 1GigE port, such as the
>> USB port or JTAG header? If so, what would be the required procedure to do
>> so?
>>
>> Thanks,
>>
>> Mark Peryer
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
> --
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Re: [casper] Unable to Load Firmware Image onto SKARAB

[Adam Isaacson]

Hi Mark,

I assume you were loading the latest BSP images to your SKARAB? Further to
what Wesley said,  please can you also indicate the following:

1) Did you reprogramme both the multiboot and golden flash images?
2) Did you use the *.hex or *.bin file that was in the repo?
3) Is it possible that you configured the multiboot image at address 0x0
and the golden image at address 0x300 instead of the multiboot image at
0x300 and the golden image at 0x0?
4) I am assuming you powered down the board after configuration?
5) Can you explain in step format how you went about configuring the flash?

Okay, so it seems the image in the flash is corrupt. Yes, it is possible to
configure the flash on your board via the JTAG and using the *.mcs files
and the Vivado hardware manager. This will involve removing the SKARAB lid
to access the connector, but let us first see if your board comes back and
what steps resulted in this issue.

Kind regards,

Adam





On Wed, Jun 14, 2017 at 11:11 PM, Wesley New  wrote:

> Hi Mark,
>
> Firstly, welcome to the CASPER community.
>
> The SKARAB has multiple images stored in Flash. These are meant only used
> for the initial FPGA image at start up and a fall back image. This is a
> Xilinx standard method of configuration. You should be using the
> upload_to_ram_and_program function. This function uploads the your compiled
> fpg file to the SDRAM and then triggers the Virtex to program itself from
> the SDRAM. You will probably have overwritten the boot images. :(
>
> import casperfpga
>
> SKARAB_IP = '10.99.45.170'
> SKARAB_FPG = 'skarab.fpg'
>
> # skarab programming
> skarab = casperfpga.CasperFpga(SKARAB_IP)
> skarab.upload_to_ram_and_program(SKARAB_FPG)
>
> Does the board come back after waiting some time?
>
>
>
>
> Wesley New
> South African SKA Project
> +2721 506 7300 <+27%2021%20506%207300>
> www.ska.ac.za
>
>
>
> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
> mark.per...@cfa.harvard.edu> wrote:
>
>> Hello,
>>
>> After trying to reconfigure the flash memory on the Virtex7 FPGA with a
>> new image, I am no longer able to connect to the SKARAB through casperfpga
>> using the 1GigE port. When I enter the command fpga =
>> casperfpga.SkarabFpga('169.254.128.213'), the following is output.
>>
>> DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
>> DEBUG:casperfpga.skarab_fpga:Waiting for response.
>> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
>> ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not
>> received.
>>
>> My thinking is that the firmware image loaded into the flash is corrupt
>> and now the 1GigE port is disabled. Are these any other possible ways to
>> load a firmware image into flash without using the 1GigE port, such as the
>> USB port or JTAG header? If so, what would be the required procedure to do
>> so?
>>
>> Thanks,
>>
>> Mark Peryer
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
>



-- 
[image: SKA_banner]

Best Regards / Vriendelike Groete

*Adam Isaacson*
FPGA Engineer

[image: SKA_banner][image: SKA_banner]
[image: SKA_banner]   (+27) 82 563 9602 [image: SKA_banner]   3rd Floor,
The Park, Park Road,
[image: SKA_banner]   (+27) 21 506 7300 Pinelands
[image: SKA_banner]   (+27) 21 506 7375 7405
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Re: [casper] Unable to Load Firmware Image onto SKARAB

[Wesley New]

Hi Mark,

Firstly, welcome to the CASPER community.

The SKARAB has multiple images stored in Flash. These are meant only used
for the initial FPGA image at start up and a fall back image. This is a
Xilinx standard method of configuration. You should be using the
upload_to_ram_and_program function. This function uploads the your compiled
fpg file to the SDRAM and then triggers the Virtex to program itself from
the SDRAM. You will probably have overwritten the boot images. :(

import casperfpga

SKARAB_IP = '10.99.45.170'
SKARAB_FPG = 'skarab.fpg'

# skarab programming
skarab = casperfpga.CasperFpga(SKARAB_IP)
skarab.upload_to_ram_and_program(SKARAB_FPG)

Does the board come back after waiting some time?




Wesley New
South African SKA Project
+2721 506 7300
www.ska.ac.za



On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
mark.per...@cfa.harvard.edu> wrote:

> Hello,
>
> After trying to reconfigure the flash memory on the Virtex7 FPGA with a
> new image, I am no longer able to connect to the SKARAB through casperfpga
> using the 1GigE port. When I enter the command fpga =
> casperfpga.SkarabFpga('169.254.128.213'), the following is output.
>
> DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
> DEBUG:casperfpga.skarab_fpga:Waiting for response.
> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
> DEBUG:casperfpga.skarab_fpga:Waiting for response.
> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
> DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
> DEBUG:casperfpga.skarab_fpga:Waiting for response.
> DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
> ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not received.
>
> My thinking is that the firmware image loaded into the flash is corrupt
> and now the 1GigE port is disabled. Are these any other possible ways to
> load a firmware image into flash without using the 1GigE port, such as the
> USB port or JTAG header? If so, what would be the required procedure to do
> so?
>
> Thanks,
>
> Mark Peryer
>
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[casper] Unable to Load Firmware Image onto SKARAB

[Peryer, Mark A.]

Hello,

After trying to reconfigure the flash memory on the Virtex7 FPGA with a new
image, I am no longer able to connect to the SKARAB through casperfpga
using the 1GigE port. When I enter the command fpga =
casperfpga.SkarabFpga('169.254.128.213'), the following is output.

DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not received.

My thinking is that the firmware image loaded into the flash is corrupt and
now the 1GigE port is disabled. Are these any other possible ways to load a
firmware image into flash without using the 1GigE port, such as the USB
port or JTAG header? If so, what would be the required procedure to do so?

Thanks,

Mark Peryer

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