Re: [casper] Help with timing constraint

[Andrew van der Byl]

Hi Heystek,

Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' -
this usually shows up which paths are hurting your design. Then, as James
said, start pipeling your design.

Hope this helps.

Regards,
Andrew

On Wed, Aug 26, 2020 at 10:13 AM James Smith  wrote:

> Hello Heystek,
>
> You will have to go through the timing reports and see which signal path
> is failing timing, and by how much.
>
> Once you have an idea, you will need to sprinkle delay blocks and / or
> adjust latencies in your logic to get to a point where the place-and-route
> can find a layout that satisfies timing requirements.
>
> It's a bit of a black art, always hit and miss for me.
>
> Regards,
> James
>
>
>
>
> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler 
> wrote:
>
>> Good day everyone
>>
>> I am running a design but ran into this problem:
>>
>> xflow done!
>> touch __xps/system_routed
>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
>> -error yes implementation/system.par
>> Analyzing implementation/system.par
>>
>> 
>> ERROR: 1 constraint not met.
>>
>> PAR could not meet all timing constraints. A bitstream will not be
>> generated.
>>
>> To disable the PAR timing check:
>>
>> 1> Disable the "Treat timing closure failure as error" option from the
>> Project Options dialog in XPS.
>>
>> OR
>>
>> 2> Type following at the XPS prompt:
>> XPS% xset enable_par_timing_error 0
>>
>> 
>> system.make:140: recipe for target 'implementation/system.bit' failed
>> gmake: *** [implementation/system.bit] Error 1
>> ERROR:EDK -
>>Error while running "gmake -f system.make bits".
>>
>> It seems to be a timing constraint.
>>
>> How do I deal with this?
>>
>> Thanks for the help!
>>
>> Heystek
>>
>> --
>> You received this message because you are subscribed to the Google Groups
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>> 
>> .
>>
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> 
> .
>

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Re: [casper] Help with timing constraint

[Andrew van der Byl]

Hi Heystek,

1) Navigate to your project folder
2) Then go to and open: /myproj/myproj.runs/impl_1/
top_timing_summary_routed.rpt

Just a note - this file is usually fairly large as text files go ~20MB.

Regards,
Andrew

On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler 
wrote:

> Hey James and Andrew
>
> Thank you so much for the advice!
>
> @Andrew, this might be a stupid question, but where do I locate the 
> top_timing_summary_routed.rpt
> file?
>
> Heystek
>
>
> On 26 Aug 2020, at 10:17, Andrew van der Byl  wrote:
>
> Hi Heystek,
>
> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' -
> this usually shows up which paths are hurting your design. Then, as James
> said, start pipeling your design.
>
> Hope this helps.
>
> Regards,
> Andrew
>
> On Wed, Aug 26, 2020 at 10:13 AM James Smith  wrote:
>
>> Hello Heystek,
>>
>> You will have to go through the timing reports and see which signal path
>> is failing timing, and by how much.
>>
>> Once you have an idea, you will need to sprinkle delay blocks and / or
>> adjust latencies in your logic to get to a point where the place-and-route
>> can find a layout that satisfies timing requirements.
>>
>> It's a bit of a black art, always hit and miss for me.
>>
>> Regards,
>> James
>>
>>
>>
>>
>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler 
>> wrote:
>>
>>> Good day everyone
>>>
>>> I am running a design but ran into this problem:
>>>
>>> xflow done!
>>> touch __xps/system_routed
>>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
>>> -error yes implementation/system.par
>>> Analyzing implementation/system.par
>>>
>>> 
>>> ERROR: 1 constraint not met.
>>>
>>> PAR could not meet all timing constraints. A bitstream will not be
>>> generated.
>>>
>>> To disable the PAR timing check:
>>>
>>> 1> Disable the "Treat timing closure failure as error" option from the
>>> Project Options dialog in XPS.
>>>
>>> OR
>>>
>>> 2> Type following at the XPS prompt:
>>> XPS% xset enable_par_timing_error 0
>>>
>>> 
>>> system.make:140: recipe for target 'implementation/system.bit' failed
>>> gmake: *** [implementation/system.bit] Error 1
>>> ERROR:EDK -
>>>Error while running "gmake -f system.make bits".
>>>
>>> It seems to be a timing constraint.
>>>
>>> How do I deal with this?
>>>
>>> Thanks for the help!
>>>
>>> Heystek
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" group.
>>> To unsubscribe from this group and stop receiving emails from it, send
>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DQBAuUfbk9H%3D7hOS%2BO6epcTe%2BrR7egqKecFMCrf0J9Yqg%40mail.gmail.com?utm_medium=email_source=footer>
>>> .
>>>
>>
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>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG67D36TnqUAXAufGUtsAqBCry0VMk%2BKxp%2BsHicvOu9kVsG5Aw%40mail.gmail.com?utm_medium=email_source=footer>
>> .
>>
>
>
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> &l

Re: [casper] Help with timing constraint

[Andrew van der Byl]

Hi Heystek,

It's possible that you then have another issue that causes the build
process to exit prior to generating that file. You'll need to debug that
first.

Regards,
Andrew

On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler 
wrote:

> Hey Andrew
>
> It is strange, I cant seem to locate top_timing_summary_routed.rpt
>
> I am running Matlab 2012B with ISE 14.7
>
>
>
> On 26 Aug 2020, at 10:27, Andrew van der Byl  wrote:
>
> Hi Heystek,
>
> 1) Navigate to your project folder
> 2) Then go to and open: /myproj/myproj.runs/impl_1/
> top_timing_summary_routed.rpt
>
> Just a note - this file is usually fairly large as text files go ~20MB.
>
> Regards,
> Andrew
>
> On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler 
> wrote:
>
>> Hey James and Andrew
>>
>> Thank you so much for the advice!
>>
>> @Andrew, this might be a stupid question, but where do I locate the 
>> top_timing_summary_routed.rpt
>> file?
>>
>> Heystek
>>
>>
>> On 26 Aug 2020, at 10:17, Andrew van der Byl  wrote:
>>
>> Hi Heystek,
>>
>> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' -
>> this usually shows up which paths are hurting your design. Then, as James
>> said, start pipeling your design.
>>
>> Hope this helps.
>>
>> Regards,
>> Andrew
>>
>> On Wed, Aug 26, 2020 at 10:13 AM James Smith  wrote:
>>
>>> Hello Heystek,
>>>
>>> You will have to go through the timing reports and see which signal path
>>> is failing timing, and by how much.
>>>
>>> Once you have an idea, you will need to sprinkle delay blocks and / or
>>> adjust latencies in your logic to get to a point where the place-and-route
>>> can find a layout that satisfies timing requirements.
>>>
>>> It's a bit of a black art, always hit and miss for me.
>>>
>>> Regards,
>>> James
>>>
>>>
>>>
>>>
>>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Good day everyone
>>>>
>>>> I am running a design but ran into this problem:
>>>>
>>>> xflow done!
>>>> touch __xps/system_routed
>>>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
>>>> -error yes implementation/system.par
>>>> Analyzing implementation/system.par
>>>>
>>>> 
>>>> ERROR: 1 constraint not met.
>>>>
>>>> PAR could not meet all timing constraints. A bitstream will not be
>>>> generated.
>>>>
>>>> To disable the PAR timing check:
>>>>
>>>> 1> Disable the "Treat timing closure failure as error" option from the
>>>> Project Options dialog in XPS.
>>>>
>>>> OR
>>>>
>>>> 2> Type following at the XPS prompt:
>>>> XPS% xset enable_par_timing_error 0
>>>>
>>>> 
>>>> system.make:140: recipe for target 'implementation/system.bit' failed
>>>> gmake: *** [implementation/system.bit] Error 1
>>>> ERROR:EDK -
>>>>Error while running "gmake -f system.make bits".
>>>>
>>>> It seems to be a timing constraint.
>>>>
>>>> How do I deal with this?
>>>>
>>>> Thanks for the help!
>>>>
>>>> Heystek
>>>>
>>>> --
>>>> You received this message because you are subscribed to the Google
>>>> Groups "casper@lists.berkeley.edu" group.
>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>>> To view this discussion on the web visit
>>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DQBAuUfbk9H%3D7hOS%2BO6epcTe%2BrR7egqKecFMCrf0J9Yqg%40mail.gmail.com
>>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DQBAuUfbk9H%3D7hOS%2BO6epcTe%2BrR7egqKecFMCrf0J9Yqg%40mail.gmail.com?utm_medium=email_source=footer>
>>>> .
>>>>
>>>
>>> --
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>>> To unsubscribe from this group and stop recei

Re: [casper] Help with packing data

[Andrew van der Byl]

gt;> heystekgrob...@gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>> Hey Jack
>>>>>>>>>>
>>>>>>>>>> How are you? It has been a while since we last spoke.
>>>>>>>>>>
>>>>>>>>>> I am really struggling to pack data into binary format for my
>>>>>>>>>> design. I was wondering if you have time if you can please help me 
>>>>>>>>>> with it.
>>>>>>>>>> I have no clue if what i am doing is correct and there is no one 
>>>>>>>>>> around me
>>>>>>>>>> with the knowledge to help me.
>>>>>>>>>>
>>>>>>>>>> All that I want to do is too pack a sine wave that I already
>>>>>>>>>> generated, and write it to a BRAM.
>>>>>>>>>>
>>>>>>>>>> I hope to hear from you soon!
>>>>>>>>>>
>>>>>>>>>> Heystek
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>> --
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>>>>>>>> .
>>>>>>>>
>>>>>>>
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-- 
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Re: [casper] Help with packing data

[Andrew van der Byl]

Hi Heystek,

You can pre-compute the sinusoid values and only write the 1st quarter to
BRAM. To 'lookup' values simply read out the BRAM linearly. You could use a
counter as an address generator. Keep in mind that the address space of the
BRAM (and counter) represents only 1/4 of the waveform so you would need
some logic to keep track of when to negate and flip the readout as to get
the output values in the correct order for the 2nd, 3rd and 4th quarters of
the waveform.

Regards,
Andrew



On Fri, Nov 26, 2021 at 4:14 PM Heystek Grobler 
wrote:

> Hey Andrew
>
> Yes, you read correctly, it is 602 million data points. I perhaps thought
> that I might had to shorten the amount of data points. I played around and
> the bram can comfortably handle 6020 data points and that still gives me a
> decent sine wave if I plot it.
>
> I would I implement a lookup table for interest sake?
>
> Thanks for the help!
>
> I really appreciate it!
>
> Heystek
>
> On 26 Nov 2021, at 16:02, Andrew van der Byl  wrote:
>
> Hi Heystek,
>
> It's a Friday afternoon so perhaps my eyes are deceiving me, but it looks
> like you are wanting to store 602 million data points in BRAM? don't think
> you are going to have too much luck with that. You could generate a
> relatively fine grained cosine wave and only store the first 1/4 wave of
> it. When doing the lookup you can reuse the values (essentially just
> flipping or swapping to form the remaining 2nd,3rd and 4th quarters) as
> needed to form a full waveform. To change frequency you scale your counter
> value to skip lookup entries (so essentially you work through the lookup
> faster and hence get a shorter period sinusoid). This way you will use far
> less memory and can generate different frequencies with the same lookup
> table. Amplitude can be scaled as needed.
>
> Hope this helps.
>
> Regards,
> Andrew
>
> On Fri, Nov 26, 2021 at 3:49 PM Heystek Grobler 
> wrote:
>
>> Hey Andrew
>>
>> Thank you so much for the explanation.
>>
>> Is there a way to get around it by using a similar kind of block? Or
>> should I rethink the sine wave that I generated that makes use of 602 000
>> 000 data points?
>>
>> Thanks for the help!
>>
>> Heystek
>>
>> On 26 Nov 2021, at 15:46, Andrew Martens  wrote:
>>
>> Hi Heystek
>>
>> Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit
>> address size would equate to 4G addresses, which is far larger than the
>> amount of BRAM available in the FPGA.
>>
>> Regards
>> Andrew
>>
>> On Fri, Nov 26, 2021 at 3:40 PM Heystek Grobler 
>> wrote:
>>
>>> Hey everyone.
>>>
>>> I have one last question regarding the BRAM. For my application I need
>>> an address width of 32, but I get the error that  the maximum allowable
>>> address width is 16. Is there away around this problem or a way to get the
>>> BRAM to use an address width of 32?
>>>
>>> Thanks for the help!
>>>
>>> Heystek
>>>
>>> On 25 Nov 2021, at 21:28, Dan Werthimer  wrote:
>>>
>>>
>>> hi morag.
>>>
>>> thanks for helping everyone.
>>>
>>> best wishes,
>>>
>>> dan
>>>
>>>
>>>
>>>
>>> On Thu, Nov 25, 2021 at 11:25 AM Morag Brown  wrote:
>>>
>>>> Happy to help :)
>>>>
>>>> On Thu, Nov 25, 2021 at 9:19 PM Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hey Morag!
>>>>>
>>>>> Know I understand!
>>>>>
>>>>> It is working.
>>>>>
>>>>> 
>>>>>
>>>>> Thank you so much for the help!!!
>>>>>
>>>>> Heystek
>>>>>
>>>>> On 25 Nov 2021, at 21:08, Morag Brown  wrote:
>>>>>
>>>>> Hi Heystek,
>>>>>
>>>>> Great!
>>>>>
>>>>> I think Jack mentioned in an earlier email that the maximum number
>>>>> that can be represented by a <32,31> fixed point system is 1 - 2^-31.
>>>>> Reducing the magnitude of your sinusoid so that the peak value is below
>>>>> this maximum would work. Or alternatively, scaling your values by an 
>>>>> amount
>>>>> less than 2^31 would have the same effect.
>>>>>
>>>>> Morag
>>>>>
>>>>> On Thu, Nov 25, 2021 at 8:59 PM Heystek Grobler <
>>>>> heystekg

[casper] Call for Papers: 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

[Andrew van der Byl]

Hi all,



This is a call for papers for a session on "real-time processing for radio
astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC) in
Gran Canaria, Spain, 19-24 May 2024.



Information on the conference is at:  https://www.atrasc.com/home.php



We hope you will consider submitting an abstract or paper, and present a
talk for Commission J, or a related session at URSI AT-RASC.

Submissions are due 20 January 2024.



Commision J-07: Real-time Processing for radio astronomy

Next generation radio telescopes require wider signal processing
bandwidths, faster data transport, and shorter processing timeframes while
operating on reduced power budgets. To satisfy these demands, fast data
interconnects and higher-throughput processing platforms are needed, as
well as improvements in algorithmic implementations to make newer
instruments a reality. The session for real-time processing for Radio
Astronomy (RA) include:


1) High performance digital signal processing instrumentation for radio
astronomy, e.g. correlators, beamformers, spectrometers, pulsar and FRB
machines, and real-time RFI detection and mitigation

2) Hardware and software for these digital backends (FPGA, RFSoC, GPU, CPU,
SOM, ADC boards)

3) Software and hardware for high bandwidth data transport (e.g.
transporting data over Ethernet to GPUs)

4) Novel algorithms or techniques for real-time signal processing

5) Energy efficiency studies and optimization techniques

6) Architectures and development tools for all of the above



We hope to see you in Gran Canaria, Spain. Please feel free to distribute
this call far and wide to anyone you think may be interested!



Best Wishes,



Session organising committee


https://www.atrasc.com/home.php

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[casper] Call for Papers: 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

[Andrew van der Byl]

Hi all,



This is a call for papers for a session on "real-time processing for radio
astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC) in
Gran Canaria, Spain, 19-24 May 2024.



Information on the conference is at:  https://www.atrasc.com/home.php



We hope you will consider submitting an abstract or paper, and present a
talk for Commission J, or a related session at URSI AT-RASC.

Submissions are due *20 January 2024*.



Commision J-07: Real-time Processing for radio astronomy

Next generation radio telescopes require wider signal processing
bandwidths, faster data transport, and shorter processing timeframes while
operating on reduced power budgets. To satisfy these demands, fast data
interconnects and higher-throughput processing platforms are needed, as
well as improvements in algorithmic implementations to make newer
instruments a reality. The session for real-time processing for Radio
Astronomy (RA) include:


1) High performance digital signal processing instrumentation for radio
astronomy, e.g. correlators, beamformers, spectrometers, pulsar and FRB
machines, and real-time RFI detection and mitigation

2) Hardware and software for these digital backends (FPGA, RFSoC, GPU, CPU,
SOM, ADC boards)

3) Software and hardware for high bandwidth data transport (e.g.
transporting data over Ethernet to GPUs)

4) Novel algorithms or techniques for real-time signal processing

5) Energy efficiency studies and optimization techniques

6) Architectures and development tools for all of the above



We hope to see you in Gran Canaria, Spain. Please feel free to distribute
this call far and wide to anyone you think may be interested!



Best Wishes,



Session organising committee


https://www.atrasc.com/home.php

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[casper] 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

[Andrew van der Byl]

Hi all,



This is a FINAL call for papers for a session on "Real-time Processing for
Radio Astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC)
in Gran Canaria, Spain, 19-24 May 2024.



Information on the conference is at:  https://www.atrasc.com/home.php



We hope you will consider submitting an abstract or paper, and present a
talk for Commission J, or a related session at URSI AT-RASC.

Submissions deadline: 1 February 2024 *(DEADLINE EXTENDED!)*


We hope to see you in Gran Canaria, Spain. Please feel free to distribute
this call far and wide to anyone you think may be interested!



Best Wishes,



Session organising committee

https://www.atrasc.com/home.php




Commision J-07: Real-time Processing for Radio Astronomy

Next generation radio telescopes require wider signal processing
bandwidths, faster data transport, and shorter processing timeframes while
operating on reduced power budgets. To satisfy these demands, fast data
interconnects and higher-throughput processing platforms are needed, as
well as improvements in algorithmic implementations to make newer
instruments a reality. The session for real-time processing for Radio
Astronomy (RA) include:


1) High performance digital signal processing instrumentation for radio
astronomy, e.g. correlators, beamformers, spectrometers, pulsar and FRB
machines, and real-time RFI detection and mitigation

2) Hardware and software for these digital backends (FPGA, RFSoC, GPU, CPU,
SOM, ADC boards)

3) Software and hardware for high bandwidth data transport (e.g.
transporting data over Ethernet to GPUs)

4) Novel algorithms or techniques for real-time signal processing

5) Energy efficiency studies and optimization techniques

6) Architectures and development tools for all of the above

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[casper] Fwd: Postdoc Position in "Experimental Radio Interferometry"

[Andrew van der Byl]

Apologies for any repeat postings. Forwarding in case any casperites may be
interested.

Regards,

-- Forwarded message -
From: Matthias Kadler 
Date: Fri, Jan 26, 2024 at 12:41 AM
Subject: Fwd: Postdoc Position in "Experimental Radio Interferometry"

I am currently looking for a postdoc to work on technical developments and
tests with the SKA-MPG prototype telescope and MeerKAT. The goal of this
project would be to make a contribution towards future use of both new
facilities in international VLBI arrays.

Thanks,

Matthias

-- 
Prof. Dr. Matthias Kadler
Institut für Theoretische Physik und Astrophysik
Universität Würzburg
Campus Hubland Nord
Emil-Fischer-Str. 31
97074 Würzburg, Germany
Tel.: +49 (0)931 31 85138

-- Postdoctoral Position in Experimental Radio Interferometry
HideSubmission Information 
Publish Date:
Wednesday, January 10, 2024
Archive Date:
Wednesday, February 7, 2024
To event remaining 27 days
HideJob Summary 
Job Category:
Post-doctoral Positions and Fellowships
Institution Classification/Type:
Foreign
Institution/Company:
Julius-Maximilians-Universitaet Wuerzburg
Department Name:
Lehrstuhl fuer Astronomie
Street Line 1:
Emil-Fischer-Strasse 31
City:
Wuerzburg
State/Province:
Bavaria
Zip/Postal:
D-97074
Country:
Germany
HideAnnouncement 
Job Announcement Text:

We invite applications for a postdoctoral position in experimental radio
interferometry. We are specifically looking for a person with an interest
and experience in experimental new observing modes on novel world-class
radio-astronomical facilities. Technical development work is central to the
scope of the position and scientific participation is encouraged within the
*TANAMI* program, which studies the parsec-scale structure and emission of
relativistic jets in active galaxies.

The successful candidate will work on the project *„Southern-Hemisphere
VLBI“* within the *D-MeerKAT consortium* in the group of Matthias Kadler at
Julius-Maximilians-University Würzburg. The project will strive to support
the development of VLBI observing-mode capability on the SKA-MPG prototype
telescope and the phased MeerKAT array. It will be closely coordinated with
other projects within the D-MeerKAT consortium on complementary aspects of
science and observations with these new facilities. Specifically, a close
collaboration with colleagues at the Max Planck Institute for Radio
Astronomy (MPIfR) in Bonn, Germany, and at the South African Radio
Astronomy Observatory (SARAO) is foreseen.

Demonstrated experience in the development, testing and/or commissioning of
radio-interferometric facilities and equipment will be considered a strong
asset. Exceptional doctoral applicants with strong background will also be
considered for the position.

The position shall be filled as soon as possible. Applications received by
February 09, 2024 will be given full consideration. The position will,
however, remain open after this first deadline until a suitable
candidate is found.

All applications should include a short summary of research interests, a
CV, and contact details of two potential referees.
HidePay Compensation 
Salary Min:
$59785.00 (USD)
Salary Max:
$61682.00 (USD)
Compensation Notes:
Brutto numbers. Taxes and health insurance (15.5%) will be deduced
according to German law.
Included Benefits:

The salary will be based on the German federal public service salary scale
(E13 TV-L). Successful candidates will receive standard unemployment,
health, and retirement benefits according to the German law.

We value equality and diversity in research and encourage women and members
of other underrepresented groups to apply. Preference will also be given to
people with disabilities in case of equivalent qualification. The process
of hiring the selected candidates will be handled by the central
administration of JMU
Application Deadline:
Friday, February 9, 2024
Selection Deadline:
Thursday, February 29, 2024
Current Status of Position:
Accepting Applicants
HideApply to Job 
Attention To:
Prof. Dr. Matthias Kadler
Title:
Professor for Astrophysics
Institution/Company:
Julius-Maximilians-Universitaet Wuerzburg
Department Name:
Lehrstuhl fuer Astronomie
Street Line 1:
Emil-Fischer-Strasse 31
City:
Wuerzburg
State/Province:
Bavaria
Zip/Postal Code:
D-97074
Country:
Germany
Phone:
+49 931 31 85138
Email:
matthias.kad...@astro.uni-wuerzburg.de
HideInquiries About Job 
Attention To:
Prof. Dr. Matthias Kadler
Subject:
D-MeerKAT VLBI
Email:
matthias.kad...@astro.uni-wuerzburg.de



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