Enable USB and boot on hard drive got error messages
Hi, Friends, When I boot up the system with USB enabled and one USB drive on the board. I got following errors if boot on the hard drive file system. I didn't see this error if boot the same kernal on NFS file system. Here is the error message: kobject_register failed for scsi_mod (-17) register_blkdev: cannot get major 8 for sd register_blkdev: cannot get major 65 for sd register_blkdev: cannot get major 66 for sd register_blkdev: cannot get major 67 for sd register_blkdev: cannot get major 68 for sd register_blkdev: cannot get major 69 for sd register_blkdev: cannot get major 70 for sd register_blkdev: cannot get major 71 for sd register_blkdev: cannot get major 128 for sd register_blkdev: cannot get major 129 for sd register_blkdev: cannot get major 130 for sd register_blkdev: cannot get major 131 for sd register_blkdev: cannot get major 132 for sd register_blkdev: cannot get major 133 for sd register_blkdev: cannot get major 134 for sd register_blkdev: cannot get major 135 for sd FATAL: Error inserting sd_mod (/lib/modules/2.6.10_mvl401-davinci_evm/kernel/drivers/scsi/sd_mod.ko): No such device scsi [success] I checked both the hard drive and the NFS file system, no sd_mod.ko on both. I'm just wondering why it gives error when boot on the hard drive. Although I got this error, I could still mount the USB drive and list the files on it. But when I write a big file to the USB drive, I got a lot of system errors and it fails. Does anyone know the reason? Thanks, Lewis _ Shed those extra pounds with MSN and The Biggest Loser! http://biggestloser.msn.com/___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Unable to compile kernel (cfide_lbus_probe)
Hello, while compiling the kernel (on windows/cygwin) I get while executing make: drivers/built-in.o(.text+0x5d4b0): In function `cfide_lbus_probe': xtkbd.c: undefined reference to `cfide_platform_mmiops' drivers/built-in.o(.text+0x5d56c):xtkbd.c: undefined reference to `cfide_selectproc' make: *** [.tmp_vmlinux1] Error 1 How can I solve this? Bye ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: Turn on DSP power domain fail
Hi,
thanks for your quickly reply.
after i trying that, it still hangs at
while( !(PSC_EPCPR 0x2) ); --- always loop in here
i noticed that Advisory 1.3.22 is for hanging up in polling PTSTAT.
but in my case, it hangs
up in polling EPCPR.
do you know what may make this happen? or are there any jumper or switch i
should configure before ARM boot DSP?
by the way, what is the first step of DSP domain power on mentioned in
TMS320DM644x DMSoC ARM Subsystem(sprue14a.pdf) section13.5.2.1 mean?
step1 :
Apply power to the power pins (VDDDSP) of the DSP power domain. In this
step, the ARM
coordinates with an external device (for example, microcontroller) to supply
power to the power
pins.
thanks for your help
best,
kashin lin
2008/1/23, Arie Muijnck [EMAIL PROTECTED]:
We do something BEFORE your code:
//- Clear reserved register 0x01C41A20 to prevent hangup on PTSTAT
testing.
//(Errata SPRUZ241D Advisory 1.3.22)
PSC-MDCTL[16] = 0;
//- Put the C64x+ Core into reset (if it's on)
PSC-MDCTL[39] = (~0x0100); // ask reset
psc_update(DOMAIN_DSP);// do transition
while ((PSC-MDSTAT[39]) (0x0100)) // wait for reset seen
{
}
Arie de Muijnck
--
*From:* [EMAIL PROTECTED] [mailto:
[EMAIL PROTECTED] *On Behalf Of *kashin
Lin
*Sent:* Wednesday, January 23, 2008 09:24
*To:* davinci-linux-open-source@linux.davincidsp.com
*Subject:* Turn on DSP power domain fail
Hi,
when i try to use ARM boot DSP mode to boot my system, i got some
problem.
the platform i used is Davinci DVM6446
fisrt, i
check the switch s3 on board and be sure the s3-4's (COUT3) status is off.
then i write some code to turn on the DSP's power domain and setting the
DSPBOOTADDR
to starting address which sequence are refer to sprue14a.pdf section
13.5.2.1 .
the power on DSP's codes snip :
int
power_on_enable_dsp()
{
/* wait for previous initial finish */
while( PSC_PTSTAT GOSTAT_DSP_MASK )
;
/* set DSP power domain on */
PSC_PDCTL1 |= 0x1;
/* set DSP module enable */
PSC_MDCTL39 |= 0x3;
/* start to transit to next state */
PSC_PTCMD |= 0x2;
/* wait for power applying to DSP */
while( !PSC_EPCPR EPC_DSP_MASK ) --- always loop in here
;
/* short the power rails of the AlwaysOn
and DSP power domains. */
SCM_CHP_SHRTSW |= 0x1;
/* indicate power has been applied */
PSC_PDCTL1 |= 0x100;
/* wait for transition finish */
while( PSC_PTSTAT GOSTAT_DSP_MASK )
;
return 1;
}
it seems the EPC bit in EPCCPR register of PSC doesn't be set to 1 which
means the power hasn't been applied.
i wonder if the sequence in code is wrong? or are there any thing i should
take care?
thanks in advance~
best,
kashin lin
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Capturing NTSC video (DVEM)
Hi, Can any one help me by guiding what to do for capturing the video in NTSC format with 720x240 resolution at 30 fps. Regards, Rajen V. Joshi Embedded Engineer (CFG) -- eInfochips Business Disclaimer: This message may contain confidential, proprietary or legally Privileged information. In case you are not the original intended Recipient of the message, you must not, directly or indirectly, use, Disclose,distribute, print, or copy any part of this message and you are requested to delete it and inform the sender. Any views expressed in this message are those of the individual sender unless otherwise stated.Nothing contained in this message shall be construed as an offer or acceptance of any offer by eInfochips Limited and/or eInfochips Inc(“eInfochips”) unless sent with that express intent and with due authority of eInfochips.EInfochips has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DMA transfer from ARM RAM
Hello,
I want to use EDMA during booting. So i am testing data transfer from
ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying
from arm to ddr2, every (29-31)th bytes are broken. Any ideas?
As the base application i use spraai0-application. Here is the patch for it:
diff -uNr uartapp/dm644x.h Quartapp/dm644x.h
--- uartapp/dm644x.h2006-11-15 13:39:28.0 +0300
+++ Quartapp/dm644x.h 2008-01-24 15:33:09.0 +0300
@@ -180,6 +180,72 @@
#define DDR_TEST_PATTERN 0xA55AA55Au
#define DDR_RAM_SIZE 0x1000u
+/*
+DMA register structure
+--*/
+
+#define DMA_REG_BASE 0x01C0
/*base for dma registers*/
+
+#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000)
/*base for PaRAM sets*/
+#define PARAM_SET_OFFSET 0x20
/*offset between PaRAM stes*/
+#define PARAM_SET(n) (PARAM_SET_BASE + n * PARAM_SET_OFFSET) /*PaRAM
set n*/
+
+#define DMA_DRAE (0x0340 + DMA_REG_BASE)
/*Region access
enable. low part*/
+#define DMA_DRAE_H (0x0344 + DMA_REG_BASE)
/*Region access
enable*. high part*/
+
+#define DMA_IPR(0x1068 + DMA_REG_BASE)
/*Interrupt pending
register. low part*/
+#define DMA_IPR_H (0x106C + DMA_REG_BASE)
/*Interrupt pending
register. high part*/
+
+#define DMA_EMR(0x0300 + DMA_REG_BASE)
/*Event missed. low part*/
+#define DMA_EMR_H (0x0304 + DMA_REG_BASE)
/*Event missed. high part*/
+
+#define DMA_CCERR (0x0318 + DMA_REG_BASE)
/*Error*/
+
+#define DMA_SER(0x1038 + DMA_REG_BASE)
/*Secondary event. low part*/
+#define DMA_SER_H (0x103C + DMA_REG_BASE)
/*Secondary event. high part*/
+
+#define DMA_SECR (0x1040 + DMA_REG_BASE)
/*Secondary event
clear. low part*/
+#define DMA_SECR_H (0x1044 + DMA_REG_BASE)
/*Secondary event
clear. high part*/
+
+#define DMA_ICR(0x1070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert*/
+#define DMA_ICR_H (0x1074 + DMA_REG_BASE)
/*Interrupt clear
register. high part*/
+
+#define DMA_IESR (0x1060 + DMA_REG_BASE)
/*Interrupt set
enable. low part*/
+#define DMA_IESR_H (0x1064 + DMA_REG_BASE)
/*Interrupt set
enable. high part*/
+
+#define DMA_ESR(0x1010 + DMA_REG_BASE)
/*Event set. low part*/
+#define DMA_ESR_H (0x1014 + DMA_REG_BASE)
/*Event set. high part*/
+
+#define DMA_IPR_0 (0x2068 + DMA_REG_BASE)
/*Interrupt pending
register. low part. region 0*/
+#define DMA_IPR_H_0(0x206C + DMA_REG_BASE)
/*Interrupt pending
register. high part. region 0*/
+
+#define DMA_ICR_0 (0x2070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert. region 0*/
+#define DMA_ICR_H_0(0x2074 + DMA_REG_BASE)
/*Interrupt clear
register. high part. region 0*/
+
+#define DMA_IER_0 (0x2050 + DMA_REG_BASE)
/*Interrupt enable.
low part. region 0*/
+#define DMA_IER_H_0(0x2054 + DMA_REG_BASE)
/*Interrupt enable.
high part. region 0*/
+
+#define DMA_IESR_0 (0x2060 + DMA_REG_BASE)
/*Interrupt set
enable. low part. region 0*/
+#define DMA_IESR_H_0 (0x2064 + DMA_REG_BASE)
/*Interrupt set
enable. high part. region 0*/
+
+#define DMA_ESR_0 (0x2010 + DMA_REG_BASE)
/*Event set. low
part. region 0*/
+#define DMA_ESR_H_0(0x2014 + DMA_REG_BASE)
/*Event set. high
part. region 0*/
+
+typedef struct _dma_regs_
+{
+ volatile unsigned int OPT;
+ volatile unsigned int SRC;
+
Re: Capturing NTSC video (DVEM)
Rajen, You can capture 720x240 (progressive 30 fps) on the Davinci by setting up the V4L2 capture driver to throw away the even or odd frame interlaced frame. In the VIDIOC_S_FMT ioctl, change the v4l2_field struct member from V4L2_FIELD_INTERLACED to either V4L2_FIELD_TOP or V4L2_FIELD_BOTTOM. Here's the docs: http://v4l2spec.bytesex.org/spec-single/v4l2.html#PIXFMT http://v4l2spec.bytesex.org/spec-single/v4l2.html#VIDIOC-G-FMT http://v4l2spec.bytesex.org/spec-single/v4l2.html#V4L2-FIELD Hope that helps! David DAVID A. KONDRAD Software Design Engineer On-Q/Legrand www.onqlegrand.com ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
RE: DMA transfer from ARM RAM
Forwarding for archive :-
Thanks Vasiliev - glad working ok now.
Cheers,
~roger
-Original Message-
From: Alexander Vasiliev [mailto:[EMAIL PROTECTED]
Sent: 24 January 2008 15:10
To: Monk, Roger
Subject: Re: DMA transfer from ARM RAM
Thank you, Roger.
Now it works well.
2008/1/24, Monk, Roger [EMAIL PROTECTED]:
Hi Vasiliev,
Can you try enabling the TCM memories (via ARM CP15) and let me know
please?
/* Set CP15 to enable the DTCM and ITCM */
static void enable_tcm_cp15 (void)
{
asm (mov R0, #0x8\n
mov R0, R0, lsl #12 \n
orr R0, R0, #0x15\n
mcr p15, 0, R0, c9, c1, 0 \n
mov R0, #0x\n
orr R0, R0, #0x1\n
mcr p15, 0, R0, c9, c1, 1 : : );
return;
}
~roger
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On
Behalf Of Alexander Vasiliev
Sent: 24 January 2008 13:54
To: davinci-linux-open-source@linux.davincidsp.com
Subject: DMA transfer from ARM RAM
Hello,
I want to use EDMA during booting. So i am testing data transfer from
ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying
from arm to ddr2, every (29-31)th bytes are broken. Any ideas?
As the base application i use spraai0-application. Here is the patch
for
it:
diff -uNr uartapp/dm644x.h Quartapp/dm644x.h
--- uartapp/dm644x.h2006-11-15 13:39:28.0 +0300
+++ Quartapp/dm644x.h 2008-01-24 15:33:09.0 +0300
@@ -180,6 +180,72 @@
#define DDR_TEST_PATTERN 0xA55AA55Au
#define DDR_RAM_SIZE 0x1000u
+/*-
---
+DMA register structure
+---
---*/
+
+#define DMA_REG_BASE 0x01C0
/*base for dma registers*/
+
+#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000)
/*base for PaRAM sets*/
+#define PARAM_SET_OFFSET 0x20
/*offset between PaRAM stes*/
+#define PARAM_SET(n) (PARAM_SET_BASE + n *
PARAM_SET_OFFSET)
/*PaRAM set n*/
+
+#define DMA_DRAE (0x0340 + DMA_REG_BASE)
/*Region access
enable. low part*/
+#define DMA_DRAE_H (0x0344 + DMA_REG_BASE)
/*Region access
enable*. high part*/
+
+#define DMA_IPR(0x1068 +
DMA_REG_BASE)
/*Interrupt pending
register. low part*/
+#define DMA_IPR_H (0x106C + DMA_REG_BASE)
/*Interrupt pending
register. high part*/
+
+#define DMA_EMR(0x0300 +
DMA_REG_BASE)
/*Event missed. low part*/
+#define DMA_EMR_H (0x0304 + DMA_REG_BASE)
/*Event missed. high part*/
+
+#define DMA_CCERR (0x0318 + DMA_REG_BASE)
/*Error*/
+
+#define DMA_SER(0x1038 +
DMA_REG_BASE)
/*Secondary event. low part*/
+#define DMA_SER_H (0x103C + DMA_REG_BASE)
/*Secondary event. high part*/
+
+#define DMA_SECR (0x1040 + DMA_REG_BASE)
/*Secondary event
clear. low part*/
+#define DMA_SECR_H (0x1044 + DMA_REG_BASE)
/*Secondary event
clear. high part*/
+
+#define DMA_ICR(0x1070 +
DMA_REG_BASE)
/*Interrupt clear
register. low pert*/
+#define DMA_ICR_H (0x1074 + DMA_REG_BASE)
/*Interrupt clear
register. high part*/
+
+#define DMA_IESR (0x1060 + DMA_REG_BASE)
/*Interrupt set
enable. low part*/
+#define DMA_IESR_H (0x1064 + DMA_REG_BASE)
/*Interrupt set
enable. high part*/
+
+#define DMA_ESR(0x1010 +
DMA_REG_BASE)
/*Event set. low part*/
+#define DMA_ESR_H (0x1014 + DMA_REG_BASE)
/*Event set. high part*/
+
+#define DMA_IPR_0 (0x2068 + DMA_REG_BASE)
/*Interrupt pending
register. low part. region 0*/
+#define DMA_IPR_H_0(0x206C + DMA_REG_BASE)
/*Interrupt pending
register. high part. region 0*/
+
+#define DMA_ICR_0 (0x2070 + DMA_REG_BASE)
/*Interrupt clear
register. low pert. region 0*/
+#define DMA_ICR_H_0(0x2074 + DMA_REG_BASE)
/*Interrupt clear
register. high part. region 0*/
+
+#define DMA_IER_0 (0x2050 + DMA_REG_BASE)
/*Interrupt enable.
low part. region 0*/
+#define DMA_IER_H_0(0x2054 + DMA_REG_BASE)
/*Interrupt enable.
high part. region 0*/
+
+#define DMA_IESR_0 (0x2060 + DMA_REG_BASE)
/*Interrupt set
enable. low part. region 0*/
+#define DMA_IESR_H_0 (0x2064 + DMA_REG_BASE)
/*Interrupt set
enable. high part. region 0*/
+
+#define DMA_ESR_0 (0x2010 + DMA_REG_BASE)
/*Event set. low
part. region 0*/
+#define DMA_ESR_H_0(0x2014 + DMA_REG_BASE)
/*Event set. high
part. region 0*/
+
+typedef struct _dma_regs_
+{
+
RE: How to make CMEM cacheable on ARM side on DM6446?
Glad to hear that worked for you - not too many users of that feature
just yet!
Detailed replies inlined below...
Chris
-Original Message-
From: Kumar Brajbhushan [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 23, 2008 11:15 PM
To: Ring, Chris; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
Chris,
Thanks again. It does work. :)
Is it possible to associate this setting at algorithm level only? That
is algo A has cache enabled and B does not and both run
in the same
process.
No. Today, it's a global, per-app setting. That is, your executable
has this setting built into its binary executable image, and all 'local'
algs created by that app will use that setting.
How do you associate this setting with any particular process? Please
elaborate.
As mentioned, the setting is per-app. If you build app1 with .useCache
= true, and you build app2 with .useCache = false, they'll request
the memory for the codecs differently.
I had some more queries in previous mail. I will wait for
their answers.
Do you imply that CMEM is used for algorithm creation ONLY
when it is
local? I was under the impression that CMEM has to be used
for remote
components (DSP-side).
In general, when an app issues a *_create() call, the ti.sdo.ce.alg
package is used to grant memory to the algorithms. This ti.sdo.ce.alg
package is built into both the ARM and DSP side executables (App and
Server). In particular, in CE 2.00:
* Algs on ARM-based systems get memory via CMEM.
* Algs on DSP/BIOS-based systems get memory via DSKT2 (which
ultimately uses BIOS).
* Algs on x86-based systems get memory via malloc().
[ FYI, the above holds for CE releases prior to CE 2.00 _except_
ARM-based algs used to get memory from malloc(). We switched from
malloc() to CMEM when we realized ARM-side algs want to use HW
accelerators, and those accelerators needed physically contiguous memory
as well! ]
To restate, when the ARM-side app creates a 'local' alg, the
ti.sdo.ce.alg requests memory from CMEM to satisfy the alg requests. If
the ARM-side app creates a 'remote' alg, the _Server-side_ ti.sdo.ce.alg
requests memory from DSKT2/BIOS to satisfy the alg requests.
[ For completeness, on DM355, there are only 'local' ARM-side algs, so
all alg memory comes from CMEM. On DM6437, there are only 'local'
DSP-side algs, so all alg memory comes from DSKT2/BIOS. ]
Perhaps the confusion is that CMEM is _also_ used to allocate the app
data buffers (via Memory_allocContig()). It is true that _data_ buffers
bound for the DSP must be physically contiguous, and CMEM is typically
used for this. But again, these _app_ data buffers are different than
the _alg_ memory we're discussing.
One related query is how does CE support memory relocation? Is it
possible for application to override the memory allocated
by CE for an
algorithm on ARM-side or DSP-side?
Today, no. The alg buffers are provide by the ti.sdo.ce.alg package,
and there are no hooks for other allocators. For ARM-side algs, there
is some app-level configurability (e.g. the .useCache and .useHeap
config params), and for DSP-side algs there is even more
DSKT2/BIOS-based configurability. But currently the application cannot
supply arbitrary buffers to satisfy the alg's IALG-based, memTab
requests.
Best Regards,
Kumar
-Original Message-
From: Ring, Chris [mailto:[EMAIL PROTECTED]
Sent: Thursday, January 24, 2008 11:35 AM
To: Kumar Brajbhushan; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: How to make CMEM cacheable on ARM side on DM6446?
There is a config param in the new ti.sdo.ce.alg.Settings module, very
poorly documented in CE 2.00, but we'll have better docs in future
releases. The config param you care about is .useCache, by
default it's
false, but you can set it to true in your app's .cfg script.
Something
like:
algSettings = xdc.useModule('ti.sdo.ce.alg.Settings');
algSettings.useCache = true;
Once you set .useCache to true, all memory provided to the
ARM-side algs
will have its cache enabled - this is an app-wide flag.
(Interestingly,
apps in other processes can set this flag differently if they wish!)
[ For those following along, note that this memory is memory the _alg_
requests under the covers during the *_create() calls. We're not
talking about the data buffers which the _app_ requests. _Those_ app
buffers can also now be requested to be cached on a per-buffer basis,
using the 'params' field of the new Memory_alloc() fxn, in CE 2.00. ]
And finally, I'm not sure whether you'll stumble on any cache-related
coherency issues in your codec - if all references to that memory are
via the CPU, you should be fine.
Hope that helps!
Chris
-Original Message-
From: Kumar Brajbhushan [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 23, 2008 8:24 PM
To: Ring, Chris;
C++ Apps and Codec Engine
Hello, I'm about ready to move away from just modifying the example applications that came with the DVEVM and wanting to start creating my own from scratch. All of the example apps seem to be using arm_v5t_le-gcc. Does anybody forsee any problem with me using the arm_v5t_le-g++ compiler when I will be using and loading custom codecs. I'm not talking about compiling codecs in C++ those will still be C, but the application that uses it in C++? Thanks, Josh ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: Davinci-linux-open-source Digest, Vol 25, Issue 53
hi I am working on DM355 ,i try to porting gstreamer according to README file , but failed and got some error . Can i use the gstreamer (download from http://focus.ti.com/dsp/docs/dspsplash.tsp?contentId=3100) on my DM355 board? [EMAIL PROTECTED] wrote: Send Davinci-linux-open-source mailing list submissions to davinci-linux-open-source@linux.davincidsp.com To subscribe or unsubscribe via the World Wide Web, visit http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source or, via email, send a message with subject or body 'help' to [EMAIL PROTECTED] You can reach the person managing the list at [EMAIL PROTECTED] When replying, please edit your Subject line so it is more specific than Re: Contents of Davinci-linux-open-source digest... Today's Topics: 1. DMA transfer from ARM RAM (Alexander Vasiliev) 2. Re: Capturing NTSC video (DVEM) (David A Kondrad) 3. RE: DMA transfer from ARM RAM (Monk, Roger) 4. RE: How to make CMEM cacheable on ARM side on DM6446? (Ring, Chris) -- Message: 1 Date: Thu, 24 Jan 2008 16:54:20 +0300 From: Alexander Vasiliev [EMAIL PROTECTED] Subject: DMA transfer from ARM RAM To: davinci-linux-open-source@linux.davincidsp.com Message-ID: [EMAIL PROTECTED] Content-Type: text/plain; charset=ISO-8859-1 Hello, I want to use EDMA during booting. So i am testing data transfer from ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying from arm to ddr2, every (29-31)th bytes are broken. Any ideas? As the base application i use spraai0-application. Here is the patch for it: diff -uNr uartapp/dm644x.h Quartapp/dm644x.h --- uartapp/dm644x.h2006-11-15 13:39:28.0 +0300 +++ Quartapp/dm644x.h 2008-01-24 15:33:09.0 +0300 @@ -180,6 +180,72 @@ #define DDR_TEST_PATTERN 0xA55AA55Au #define DDR_RAM_SIZE 0x1000u +/* +DMA register structure +--*/ + +#define DMA_REG_BASE 0x01C0 /*base for dma registers*/ + +#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000) /*base for PaRAM sets*/ +#define PARAM_SET_OFFSET 0x20 /*offset between PaRAM stes*/ +#define PARAM_SET(n) (PARAM_SET_BASE + n * PARAM_SET_OFFSET) /*PaRAM set n*/ + +#define DMA_DRAE (0x0340 + DMA_REG_BASE) /*Region access enable. low part*/ +#define DMA_DRAE_H (0x0344 + DMA_REG_BASE) /*Region access enable*. high part*/ + +#define DMA_IPR(0x1068 + DMA_REG_BASE) /*Interrupt pending register. low part*/ +#define DMA_IPR_H (0x106C + DMA_REG_BASE) /*Interrupt pending register. high part*/ + +#define DMA_EMR(0x0300 + DMA_REG_BASE) /*Event missed. low part*/ +#define DMA_EMR_H (0x0304 + DMA_REG_BASE) /*Event missed. high part*/ + +#define DMA_CCERR (0x0318 + DMA_REG_BASE) /*Error*/ + +#define DMA_SER(0x1038 + DMA_REG_BASE) /*Secondary event. low part*/ +#define DMA_SER_H (0x103C + DMA_REG_BASE) /*Secondary event. high part*/ + +#define DMA_SECR (0x1040 + DMA_REG_BASE) /*Secondary event clear. low part*/ +#define DMA_SECR_H (0x1044 + DMA_REG_BASE) /*Secondary event clear. high part*/ + +#define DMA_ICR(0x1070 + DMA_REG_BASE) /*Interrupt clear register. low pert*/ +#define DMA_ICR_H (0x1074 + DMA_REG_BASE) /*Interrupt clear register. high part*/ + +#define DMA_IESR (0x1060 + DMA_REG_BASE) /*Interrupt set enable. low part*/ +#define DMA_IESR_H (0x1064 + DMA_REG_BASE) /*Interrupt set enable. high part*/ + +#define DMA_ESR(0x1010 + DMA_REG_BASE) /*Event set. low part*/ +#define DMA_ESR_H (0x1014 + DMA_REG_BASE) /*Event set. high part*/ + +#define DMA_IPR_0 (0x2068 + DMA_REG_BASE) /*Interrupt pending
Re: Davinci-linux-open-source Digest, Vol 25, Issue 53
hi I am working on DM355 ,i try to porting gstreamer according to README file , but failed and got some error . Can i use the gstreamer (download from http://focus.ti.com/dsp/docs/dspsplash.tsp?contentId=3100) on my DM355 board? [EMAIL PROTECTED] wrote: Send Davinci-linux-open-source mailing list submissions to davinci-linux-open-source@linux.davincidsp.com To subscribe or unsubscribe via the World Wide Web, visit http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source or, via email, send a message with subject or body 'help' to [EMAIL PROTECTED] You can reach the person managing the list at [EMAIL PROTECTED] When replying, please edit your Subject line so it is more specific than Re: Contents of Davinci-linux-open-source digest... Today's Topics: 1. DMA transfer from ARM RAM (Alexander Vasiliev) 2. Re: Capturing NTSC video (DVEM) (David A Kondrad) 3. RE: DMA transfer from ARM RAM (Monk, Roger) 4. RE: How to make CMEM cacheable on ARM side on DM6446? (Ring, Chris) -- Message: 1 Date: Thu, 24 Jan 2008 16:54:20 +0300 From: Alexander Vasiliev [EMAIL PROTECTED] Subject: DMA transfer from ARM RAM To: davinci-linux-open-source@linux.davincidsp.com Message-ID: [EMAIL PROTECTED] Content-Type: text/plain; charset=ISO-8859-1 Hello, I want to use EDMA during booting. So i am testing data transfer from ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying from arm to ddr2, every (29-31)th bytes are broken. Any ideas? As the base application i use spraai0-application. Here is the patch for it: diff -uNr uartapp/dm644x.h Quartapp/dm644x.h --- uartapp/dm644x.h2006-11-15 13:39:28.0 +0300 +++ Quartapp/dm644x.h 2008-01-24 15:33:09.0 +0300 @@ -180,6 +180,72 @@ #define DDR_TEST_PATTERN 0xA55AA55Au #define DDR_RAM_SIZE 0x1000u +/* +DMA register structure +--*/ + +#define DMA_REG_BASE 0x01C0 /*base for dma registers*/ + +#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000) /*base for PaRAM sets*/ +#define PARAM_SET_OFFSET 0x20 /*offset between PaRAM stes*/ +#define PARAM_SET(n) (PARAM_SET_BASE + n * PARAM_SET_OFFSET) /*PaRAM set n*/ + +#define DMA_DRAE (0x0340 + DMA_REG_BASE) /*Region access enable. low part*/ +#define DMA_DRAE_H (0x0344 + DMA_REG_BASE) /*Region access enable*. high part*/ + +#define DMA_IPR(0x1068 + DMA_REG_BASE) /*Interrupt pending register. low part*/ +#define DMA_IPR_H (0x106C + DMA_REG_BASE) /*Interrupt pending register. high part*/ + +#define DMA_EMR(0x0300 + DMA_REG_BASE) /*Event missed. low part*/ +#define DMA_EMR_H (0x0304 + DMA_REG_BASE) /*Event missed. high part*/ + +#define DMA_CCERR (0x0318 + DMA_REG_BASE) /*Error*/ + +#define DMA_SER(0x1038 + DMA_REG_BASE) /*Secondary event. low part*/ +#define DMA_SER_H (0x103C + DMA_REG_BASE) /*Secondary event. high part*/ + +#define DMA_SECR (0x1040 + DMA_REG_BASE) /*Secondary event clear. low part*/ +#define DMA_SECR_H (0x1044 + DMA_REG_BASE) /*Secondary event clear. high part*/ + +#define DMA_ICR(0x1070 + DMA_REG_BASE) /*Interrupt clear register. low pert*/ +#define DMA_ICR_H (0x1074 + DMA_REG_BASE) /*Interrupt clear register. high part*/ + +#define DMA_IESR (0x1060 + DMA_REG_BASE) /*Interrupt set enable. low part*/ +#define DMA_IESR_H (0x1064 + DMA_REG_BASE) /*Interrupt set enable. high part*/ + +#define DMA_ESR(0x1010 + DMA_REG_BASE) /*Event set. low part*/ +#define DMA_ESR_H (0x1014 + DMA_REG_BASE) /*Event set. high part*/ + +#define DMA_IPR_0 (0x2068 + DMA_REG_BASE) /*Interrupt pending
gstreamer for dm355
ok thanks I am working on DM355 ,i try to porting gstreamer according to README file ,but failed and got some error . Can i use the gstreamer (download from http://focus.ti.com/dsp/docs/dspsplash.tsp?contentId=3100) on my DM355 board? anyone can help me? thanks [EMAIL PROTECTED] wrote: Send Davinci-linux-open-source mailing list submissions to davinci-linux-open-source@linux.davincidsp.com To subscribe or unsubscribe via the World Wide Web, visit http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source or, via email, send a message with subject or body 'help' to [EMAIL PROTECTED] You can reach the person managing the list at [EMAIL PROTECTED] When replying, please edit your Subject line so it is more specific than Re: Contents of Davinci-linux-open-source digest... Today's Topics: 1. Re: Davinci-linux-open-source Digest, Vol 25, Issue 53 (mackylee) -- Message: 1 Date: Fri, 25 Jan 2008 13:12:59 +0800 From: mackylee [EMAIL PROTECTED] Subject: Re: Davinci-linux-open-source Digest, Vol 25, Issue 53 To: davinci-linux-open-source@linux.davincidsp.com Message-ID: [EMAIL PROTECTED] Content-Type: text/plain; charset=ISO-8859-1; format=flowed hi I am working on DM355 ,i try to porting gstreamer according to README file , but failed and got some error . Can i use the gstreamer (download from http://focus.ti.com/dsp/docs/dspsplash.tsp?contentId=3100) on my DM355 board? [EMAIL PROTECTED] wrote: Send Davinci-linux-open-source mailing list submissions to davinci-linux-open-source@linux.davincidsp.com To subscribe or unsubscribe via the World Wide Web, visit http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source or, via email, send a message with subject or body 'help' to [EMAIL PROTECTED] You can reach the person managing the list at [EMAIL PROTECTED] When replying, please edit your Subject line so it is more specific than Re: Contents of Davinci-linux-open-source digest... Today's Topics: 1. DMA transfer from ARM RAM (Alexander Vasiliev) 2. Re: Capturing NTSC video (DVEM) (David A Kondrad) 3. RE: DMA transfer from ARM RAM (Monk, Roger) 4. RE: How to make CMEM cacheable on ARM side on DM6446? (Ring, Chris) -- Message: 1 Date: Thu, 24 Jan 2008 16:54:20 +0300 From: Alexander Vasiliev [EMAIL PROTECTED] Subject: DMA transfer from ARM RAM To: davinci-linux-open-source@linux.davincidsp.com Message-ID: [EMAIL PROTECTED] Content-Type: text/plain; charset=ISO-8859-1 Hello, I want to use EDMA during booting. So i am testing data transfer from ARM RAM to DRR2. Copying from DRR to arm goes fine. But during copying from arm to ddr2, every (29-31)th bytes are broken. Any ideas? As the base application i use spraai0-application. Here is the patch for it: diff -uNr uartapp/dm644x.h Quartapp/dm644x.h --- uartapp/dm644x.h2006-11-15 13:39:28.0 +0300 +++ Quartapp/dm644x.h 2008-01-24 15:33:09.0 +0300 @@ -180,6 +180,72 @@ #define DDR_TEST_PATTERN 0xA55AA55Au #define DDR_RAM_SIZE 0x1000u +/* +DMA register structure +--*/ + +#define DMA_REG_BASE 0x01C0 /*base for dma registers*/ + +#define PARAM_SET_BASE (DMA_REG_BASE + 0x4000) /*base for PaRAM sets*/ +#define PARAM_SET_OFFSET 0x20 /*offset between PaRAM stes*/ +#define PARAM_SET(n) (PARAM_SET_BASE + n * PARAM_SET_OFFSET) /*PaRAM set n*/ + +#define DMA_DRAE (0x0340 + DMA_REG_BASE) /*Region access enable. low part*/ +#define DMA_DRAE_H (0x0344 + DMA_REG_BASE) /*Region access enable*. high part*/ + +#define DMA_IPR(0x1068 + DMA_REG_BASE) /*Interrupt pending register. low part*/ +#define DMA_IPR_H (0x106C + DMA_REG_BASE) /*Interrupt pending register. high part*/ + +#define DMA_EMR(0x0300 + DMA_REG_BASE) /*Event missed. low part*/ +#define DMA_EMR_H (0x0304 + DMA_REG_BASE) /*Event missed. high part*/ + +#define DMA_CCERR (0x0318 + DMA_REG_BASE) /*Error*/ + +#define DMA_SER(0x1038 + DMA_REG_BASE) /*Secondary event. low part*/ +#define DMA_SER_H
Test vectors WMA9 / VC-1 / WMV9 for davinci....
Hi All, Can somebody guide me to davinci test vectors for vc-1 / wma9 /wmv9 test vectors ? I did find some test vectors but all were for HD size. I need D1 size or 720 X 480 size vectors. Thanks in advance. Warm Regards, Ragas ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
RE: Test vectors WMA9 / VC-1 / WMV9 for davinci....
Ragas, The best option is to procure the SMPTE VC-1 Test Material: http://store.smpte.org/VC-1-Test-Material-p/vc-1.htm This contains VC-1 conformance bitstreams with D1 resolutions. Regards, Anand From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Ragas sag Sent: Friday, January 25, 2008 12:46 PM To: davinci-linux-open-source@linux.davincidsp.com Subject: Test vectors WMA9 / VC-1 / WMV9 for davinci Hi All, Can somebody guide me to davinci test vectors for vc-1 / wma9 /wmv9 test vectors ? I did find some test vectors but all were for HD size. I need D1 size or 720 X 480 size vectors. Thanks in advance. Warm Regards, Ragas ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
