Re: [Emc-users] stepgen pwmgen fixes

2008-09-23 Thread Sebastian Kuzminsky
Sebastian Kuzminsky wrote:
 Eric (and anyone else who's had problems with pwmgen), please try this:
  
 http://highlab.com/~seb/bzr/emc2/hostmot2/src/hal/drivers/mesa-hostmot2/pwmgen.c

I just committed this fix to the CVS TRUNK (along with pwmgen.frequency 
and some other minor stuff).  Let me know if this fixes pwmgens for you 
guys.


-- 
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Re: [Emc-users] stepgen pwmgen fixes

2008-09-23 Thread Eric H. Johnson
Sebastian,

Can you check to see that the pwmgen.enable is working properly. I was
running samples all day (which looked great, btw, after resolving a very odd
problem) so I did not have a chance to do much testing. I am now dropping
the enable when the shutter closes, however the pwmgen.value is still
getting values. The laser was still coming on even when the enable was low.

I will try setting the frequency of the pwm from the latest update and
hopefully test that tomorrow.

Regards,
Eric


I bet that's it then.  The hm2_5i20 pwmgen currently goes at 25 KHz with no
way to change it.  I'll add a HAL parameter and let's see if that helps.


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Re: [Emc-users] stepgen pwmgen fixes

2008-09-23 Thread Peter C. Wallace
On Tue, 23 Sep 2008, Eric H. Johnson wrote:

 Date: Tue, 23 Sep 2008 21:09:44 -0400
 From: Eric H. Johnson [EMAIL PROTECTED]
 Reply-To: Enhanced Machine Controller (EMC)
 emc-users@lists.sourceforge.net
 To: 'Enhanced Machine Controller (EMC)' emc-users@lists.sourceforge.net
 Subject: Re: [Emc-users] stepgen  pwmgen fixes
 
 Sebastian,

 Can you check to see that the pwmgen.enable is working properly. I was
 running samples all day (which looked great, btw, after resolving a very odd
 problem) so I did not have a chance to do much testing. I am now dropping
 the enable when the shutter closes, however the pwmgen.value is still
 getting values. The laser was still coming on even when the enable was low.

 I will try setting the frequency of the pwm from the latest update and
 hopefully test that tomorrow.

 Regards,
 Eric


Well I'm not Sebastian, but I know why you are seeing that behavior:

The enable register was designed for our PWM and Analog output daughter cards 
so it doesnt actually affect the PWM output, its just a group of (active low) 
output bits used to enable the daughter card output channels. I can certainly 
change this behavior so that the PWM output is forced low when a channel is 
not enabled (cheap in terms of FPGA hardware). The active low enable output is 
used to guarantee that the motor drive outputs are off at power up (or 
watchdog bite)

I dont think there are any bad side effects of forcing the PWM output low if 
disabled, but there are possible bad side effect of using a active high PWM 
output without the enable (Laser is on high at power up unless you have some 
other active low enable signal)

Peter Wallace
Mesa Electronics

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-23 Thread Sebastian Kuzminsky
Peter C. Wallace wrote:
 On Tue, 23 Sep 2008, Eric H. Johnson wrote:
 Sebastian,

 Can you check to see that the pwmgen.enable is working properly. I was
 running samples all day (which looked great, btw, after resolving a very odd
 problem) so I did not have a chance to do much testing. I am now dropping
 the enable when the shutter closes, however the pwmgen.value is still
 getting values. The laser was still coming on even when the enable was low.

 I will try setting the frequency of the pwm from the latest update and
 hopefully test that tomorrow.
 
 Well I'm not Sebastian, but I know why you are seeing that behavior:
 
 The enable register was designed for our PWM and Analog output daughter cards 
 so it doesnt actually affect the PWM output, its just a group of (active low) 
 output bits used to enable the daughter card output channels. I can certainly 
 change this behavior so that the PWM output is forced low when a channel is 
 not enabled (cheap in terms of FPGA hardware). The active low enable output 
 is 
 used to guarantee that the motor drive outputs are off at power up (or 
 watchdog bite)
 
 I dont think there are any bad side effects of forcing the PWM output low if 
 disabled, but there are possible bad side effect of using a active high PWM 
 output without the enable (Laser is on high at power up unless you have some 
 other active low enable signal)

The driver  firmware currently communicate the pwmgen.XX.enable pin to 
the /Enable IO pin on the IO connector (I just re-checked this). 
Peter's got a good argument for why the value of the PWM pin shouldnt 
matter to the downstream equipment if the /Enable IO pin is high.

Eric, how are you handling the start-up condition (and potentially the 
watchdog condition) that Peter is describing?

What would it mean to keep the PWM IO pin low if the .enable HAL pin is 
low?  Should the FPGA *not* let the PWM pin go to high-impedance/pullup 
at bootup and at watchdog bite?


-- 
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Hi meatie! How's the weather?
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Re: [Emc-users] stepgen pwmgen fixes

2008-09-23 Thread Peter C. Wallace
On Tue, 23 Sep 2008, Sebastian Kuzminsky wrote:

 Date: Tue, 23 Sep 2008 20:24:42 -0600
 From: Sebastian Kuzminsky [EMAIL PROTECTED]
 Reply-To: Enhanced Machine Controller (EMC)
 emc-users@lists.sourceforge.net
 To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net
 Subject: Re: [Emc-users] stepgen  pwmgen fixes
 
 Peter C. Wallace wrote:
 On Tue, 23 Sep 2008, Eric H. Johnson wrote:
 Sebastian,

 Can you check to see that the pwmgen.enable is working properly. I was
 running samples all day (which looked great, btw, after resolving a very odd
 problem) so I did not have a chance to do much testing. I am now dropping
 the enable when the shutter closes, however the pwmgen.value is still
 getting values. The laser was still coming on even when the enable was low.

 I will try setting the frequency of the pwm from the latest update and
 hopefully test that tomorrow.

 Well I'm not Sebastian, but I know why you are seeing that behavior:

 The enable register was designed for our PWM and Analog output daughter cards
 so it doesnt actually affect the PWM output, its just a group of (active low)
 output bits used to enable the daughter card output channels. I can certainly
 change this behavior so that the PWM output is forced low when a channel is
 not enabled (cheap in terms of FPGA hardware). The active low enable output 
 is
 used to guarantee that the motor drive outputs are off at power up (or
 watchdog bite)

 I dont think there are any bad side effects of forcing the PWM output low if
 disabled, but there are possible bad side effect of using a active high PWM
 output without the enable (Laser is on high at power up unless you have some
 other active low enable signal)

 The driver  firmware currently communicate the pwmgen.XX.enable pin to
 the /Enable IO pin on the IO connector (I just re-checked this).
 Peter's got a good argument for why the value of the PWM pin shouldnt
 matter to the downstream equipment if the /Enable IO pin is high.

 Eric, how are you handling the start-up condition (and potentially the
 watchdog condition) that Peter is describing?

 What would it mean to keep the PWM IO pin low if the .enable HAL pin is
 low?  Should the FPGA *not* let the PWM pin go to high-impedance/pullup
 at bootup and at watchdog bite?


The PWM pin would only be forced low when the channel is disabled in the PWM 
enable register. After Watchdog bite and at bootup, all I/Os would be in the 
high state.

Still think best is to use the active low PWM enable output as separate 
hardware enable, perhaps moved to one of the GPIO pins if a 7I37 is used to 
enable the laser.



Peter Wallace
Mesa Electronics

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Eric H. Johnson
Sebastian,

I am not sure what you mean by the FPGA register. Do you mean the interface
register between the driver and the m5i20, or the register actually handling
the PWM within the FPGA? As I said in an earlier email (off list), I concur
that the value being sent to the FPGA through the interface register is
correct (providing the bit shift to bits 16-27 is where the value is
supposed to go), which would confirm that my pwmgen.scale is set to 1.0.

I was able to measure the duty cycle on a pain old multi-meter. At values of
0.125 and below, the voltage would start dropping from the almost 100% duty
cycle voltage of just under 3.3V, and very linearly for the range of 0.125
down to 0.0. The voltage reading from my meter was in fact very accurate.

Here are the voltage readings I got:

ValueVoltage
=0.126   3.278
0.125 3.272
0.120 3.144
0.110 2.884
0.100 2.623
0.090 2.362
0.080 2.102 
0.070 1.841
0.060 1.580
0.050 1.320
0.040 1.059
0.030 0.798
0.020 0.538
0.010 0.278

Regards,
Eric


How are you measuring duty cycle?

I'm confident that (at least in my test setup) setting pwmgen.XX.value
causes the correct number to be set in the FPGA register.

Take a look at http://pastebin.ca/1208030.  I updated pwmgen.c to decode
the number in the PWM Value Register, then used raw.dump-state to show the
register when pwmgen.value was -1.0 to +0.3 in increments of 0.1.  Lines
1-22 show the relevant dmesg output for .value=0, then I just show the PWM
Value Register for the other .value settings.

In addition to the correct numbers being set in the register, the
corresponding LED on the 7i31 LED Debug board varies in intensity as
expected, and the small DC servo (driven by a 7i30 servo amp) changes its
speed as expected.

I'm not sure why you're seeing what you're seeing.  Is maybe your
pwmgen.scale not set to 1.0?


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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Kim Mortensen
Field Programable Gate Array.

is a programmable chip.

Best Regards
Kim Mortensen

2008/9/22 Eric H. Johnson [EMAIL PROTECTED]

 Sebastian,

 I am not sure what you mean by the FPGA register. Do you mean the interface
 register between the driver and the m5i20, or the register actually
 handling
 the PWM within the FPGA? As I said in an earlier email (off list), I concur
 that the value being sent to the FPGA through the interface register is
 correct (providing the bit shift to bits 16-27 is where the value is
 supposed to go), which would confirm that my pwmgen.scale is set to 1.0.

 I was able to measure the duty cycle on a pain old multi-meter. At values
 of
 0.125 and below, the voltage would start dropping from the almost 100% duty
 cycle voltage of just under 3.3V, and very linearly for the range of 0.125
 down to 0.0. The voltage reading from my meter was in fact very accurate.

 Here are the voltage readings I got:

 ValueVoltage
 =0.126   3.278
 0.125 3.272
 0.120 3.144
 0.110 2.884
 0.100 2.623
 0.090 2.362
 0.080 2.102
 0.070 1.841
 0.060 1.580
 0.050 1.320
 0.040 1.059
 0.030 0.798
 0.020 0.538
 0.010 0.278

 Regards,
 Eric


 How are you measuring duty cycle?

 I'm confident that (at least in my test setup) setting pwmgen.XX.value
 causes the correct number to be set in the FPGA register.

 Take a look at http://pastebin.ca/1208030.  I updated pwmgen.c to decode
 the number in the PWM Value Register, then used raw.dump-state to show the
 register when pwmgen.value was -1.0 to +0.3 in increments of 0.1.  Lines
 1-22 show the relevant dmesg output for .value=0, then I just show the PWM
 Value Register for the other .value settings.

 In addition to the correct numbers being set in the register, the
 corresponding LED on the 7i31 LED Debug board varies in intensity as
 expected, and the small DC servo (driven by a 7i30 servo amp) changes its
 speed as expected.

 I'm not sure why you're seeing what you're seeing.  Is maybe your
 pwmgen.scale not set to 1.0?


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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Sebastian Kuzminsky
Eric H. Johnson wrote:
 I am not sure what you mean by the FPGA register. Do you mean the interface
 register between the driver and the m5i20, or the register actually handling
 the PWM within the FPGA? As I said in an earlier email (off list), I concur
 that the value being sent to the FPGA through the interface register is
 correct (providing the bit shift to bits 16-27 is where the value is
 supposed to go), which would confirm that my pwmgen.scale is set to 1.0.

By FPGA register i mean the register on the 5i20 board where the 
driver on the PC tells the 5i20 what PWM duty cycle it wants.  I think 
this means both of the things you described.

Ok so we're in agreement that the proper PWM value is being requested of 
the 5i20 board, and the question now is whether the FPGA outputs the 
proper PWM signal.


 I was able to measure the duty cycle on a pain old multi-meter. At values of
 0.125 and below, the voltage would start dropping from the almost 100% duty
 cycle voltage of just under 3.3V, and very linearly for the range of 0.125
 down to 0.0. The voltage reading from my meter was in fact very accurate.

It is my understanding that a normal voltage meter is not a reliable 
tool for measuring the pulse width of a PWM signal.

I'll see if I can borrow an oscilloscope from work...


-- 
Sebastian Kuzminsky
   Theo: Julian? I haven't seen you in twenty years. You look good.
  The picture the police have of you doesn't do you justice.
 Julian: What do the police know about justice?

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Peter C. Wallace
On Mon, 22 Sep 2008, Sebastian Kuzminsky wrote:

 Date: Mon, 22 Sep 2008 07:26:19 -0600
 From: Sebastian Kuzminsky [EMAIL PROTECTED]
 Reply-To: Enhanced Machine Controller (EMC)
 emc-users@lists.sourceforge.net
 To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net
 Subject: Re: [Emc-users] stepgen  pwmgen fixes
 
 Eric H. Johnson wrote:
 I am not sure what you mean by the FPGA register. Do you mean the interface
 register between the driver and the m5i20, or the register actually handling
 the PWM within the FPGA? As I said in an earlier email (off list), I concur
 that the value being sent to the FPGA through the interface register is
 correct (providing the bit shift to bits 16-27 is where the value is
 supposed to go), which would confirm that my pwmgen.scale is set to 1.0.

 By FPGA register i mean the register on the 5i20 board where the
 driver on the PC tells the 5i20 what PWM duty cycle it wants.  I think
 this means both of the things you described.

 Ok so we're in agreement that the proper PWM value is being requested of
 the 5i20 board, and the question now is whether the FPGA outputs the
 proper PWM signal.


 I was able to measure the duty cycle on a pain old multi-meter. At values of
 0.125 and below, the voltage would start dropping from the almost 100% duty
 cycle voltage of just under 3.3V, and very linearly for the range of 0.125
 down to 0.0. The voltage reading from my meter was in fact very accurate.

 It is my understanding that a normal voltage meter is not a reliable
 tool for measuring the pulse width of a PWM signal.

 I'll see if I can borrow an oscilloscope from work...




My experience is that most DVMs and even analog VOMs tend to read PWM average 
pretty well when set to read DC volts. This is because DVM DC input circuits 
usually include a low pass filter that does a good job of averaging the PWM 
and analog VOMs meter mechanics do the same thing.

The symptoms sound like you are running in 9 bit PWM mode (but the driver 
expecting 12 bit PWM behaviour), that is the PWM width register ends up being 
00b instead of the desired 11b. This could be because the driver does not 
initialize it or manages to overwrite the width field in the mode register 
after its been set.

It could also be a FPGA firmware error, but I checked the HostMot2 firmware 
fairy thoroughly this February, I can do some low level poking and check this 
today. (Looking at my coffee cup that says Don't look at me, Its clearly a 
software problem)



 -- 
 Sebastian Kuzminsky
   Theo: Julian? I haven't seen you in twenty years. You look good.
  The picture the police have of you doesn't do you justice.
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Mesa Electronics

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Sebastian Kuzminsky
Peter C. Wallace wrote:
 The symptoms sound like you are running in 9 bit PWM mode (but the driver 
 expecting 12 bit PWM behaviour), that is the PWM width register ends up being 
 00b instead of the desired 11b. This could be because the driver does not 
 initialize it or manages to overwrite the width field in the mode register 
 after its been set.

Eric, could you set your machine up in the way it is when PWM is 
misbehaving for you, the setp hm2_5i20.0.raw.dump-state 1, then 
pastebin the relevant part of the dmesg?  That'll show (among other 
useful things) what pwm width the hm2 driver thinks it's running in.

FWIW, the dmesg info i pastebinned last night 
(http://pastebin.ca/1208030) shows the PWM Mode register set to 0x23, 
which means 12-bit PWM, sawtooth (not symmetrical), normal 
sign/magnitude on the normal pins, double buffer mode.  I'm curious 
if yours is somehow set differently.


-- 
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  The picture the police have of you doesn't do you justice.
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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Peter C. Wallace
On Mon, 22 Sep 2008, Sebastian Kuzminsky wrote:

 Date: Mon, 22 Sep 2008 09:52:09 -0600
 From: Sebastian Kuzminsky [EMAIL PROTECTED]
 Reply-To: Enhanced Machine Controller (EMC)
 emc-users@lists.sourceforge.net
 To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net
 Subject: Re: [Emc-users] stepgen  pwmgen fixes
 
 Eric H. Johnson wrote:
 I realize that a voltmeter may not be a reliable means of measuring a PWM,
 but my particular voltmeter does seem to agree with the power output of the
 laser. It also agrees with the voltages I read when using the standard m5i20
 driver, which is already known to produce good values.

 Thus, given the consistency and linearity of the readings, I am fairly
 confident that they reasonably reflect what is going on with the PWM output.

 Peter, do you have any input on this?  I think an oscilloscope trace of
 the PWM pin being driven by the hostmot2 driver is needed to move
 forward on this issue.


SVST8_4.BIT (2/01/08)

MD5 (SVST8_4.BIT) = dcf2cabf2a4b3fc08d8b783bbaaddeab

Heres my little test batch file:


wpo 1100 00fc0fc0   ; enable outputs
wpo 1200 00fc0fc0   ; select alternate sources
wpo 4200    ; PWM rate max
wpo 4400    : turn on enables

wpo 4100 20 ; 9 bit pwm mode
wpo 4000 0100   ; 1/2 way up = 256
pause
ok = 50% duty cycle at 195.31 KHz

wpo 4100 21 ; 10 bit PWM mode
wpo 4000 0200   ; 1/2 way up = 512
pause
ok = 50% duty cycle at 97.66 KHz

wpo 4100 22 ; 11 bit PWM mode
wpo 4000 0400   ; 1/2 way up = 1024
pause
ok = 50% duty cycle at 48.83 Khz

wpo 4100 23 ; 12 bit PWM mode
wpo 4000 0800   ; 1/2 way up = 2048
pause
ok = 50% duty cycle at 24.41 Khz


All looks to be OK




Peter Wallace
Mesa Electronics

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Sebastian Kuzminsky
Peter C. Wallace wrote:
 On Mon, 22 Sep 2008, Sebastian Kuzminsky wrote:
 Eric H. Johnson wrote:
 I realize that a voltmeter may not be a reliable means of measuring a PWM,
 but my particular voltmeter does seem to agree with the power output of the
 laser. It also agrees with the voltages I read when using the standard m5i20
 driver, which is already known to produce good values.

 Thus, given the consistency and linearity of the readings, I am fairly
 confident that they reasonably reflect what is going on with the PWM output.
 Peter, do you have any input on this?  I think an oscilloscope trace of
 the PWM pin being driven by the hostmot2 driver is needed to move
 forward on this issue.

 
 SVST8_4.BIT (2/01/08)
 
 MD5 (SVST8_4.BIT) = dcf2cabf2a4b3fc08d8b783bbaaddeab

This is the same md5sum as the mesa-hostmot2/firmware/5i20/SVST8_4.BIT 
in our CVS tree.


 Heres my little test batch file:
 
 
 wpo 1100 00fc0fc0 ; enable outputs
 wpo 1200 00fc0fc0 ; select alternate sources
 wpo 4200  ; PWM rate max
 wpo 4400  : turn on enables
 
 wpo 4100 20   ; 9 bit pwm mode
 wpo 4000 0100 ; 1/2 way up = 256
 pause
 ok = 50% duty cycle at 195.31 KHz
 
 wpo 4100 21   ; 10 bit PWM mode
 wpo 4000 0200 ; 1/2 way up = 512
 pause
 ok = 50% duty cycle at 97.66 KHz
 
 wpo 4100 22   ; 11 bit PWM mode
 wpo 4000 0400 ; 1/2 way up = 1024
 pause
 ok = 50% duty cycle at 48.83 Khz
 
 wpo 4100 23   ; 12 bit PWM mode
 wpo 4000 0800 ; 1/2 way up = 2048
 pause
 ok = 50% duty cycle at 24.41 Khz
 
 
 All looks to be OK

Great to hear.

Peter's test does raw I/O with the 5i20 to cause it to output the PWM 
signal, so there's still a possibility that the hostmot2 driver does a 
different pattern of I/O which results in an incorrect waveform output. 
  I've found a scope I can borrow, I'll do a similar test using the 
hostmot2 driver tonight or another night later this week.

Does anyone know what the PWM frequency of the old m5i20 driver is?


-- 
Sebastian Kuzminsky
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  The picture the police have of you doesn't do you justice.
 Julian: What do the police know about justice?

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Eric H. Johnson
Sebastian,

It is specified as a parameter to the driver, up to 33Khz IIRC. I was
setting it to 5Khz.

Regards,
Eric

Does anyone know what the PWM frequency of the old m5i20 driver is?



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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Sebastian Kuzminsky
Eric H. Johnson wrote:
 It is specified as a parameter to the driver, up to 33Khz IIRC. I was
 setting it to 5Khz.

I bet that's it then.  The hm2_5i20 pwmgen currently goes at 25 KHz with 
no way to change it.  I'll add a HAL parameter and let's see if that helps.


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Re: [Emc-users] stepgen pwmgen fixes

2008-09-22 Thread Sebastian Kuzminsky
Eric (and anyone else who's had problems with pwmgen), please try this:
 
http://highlab.com/~seb/bzr/emc2/hostmot2/src/hal/drivers/mesa-hostmot2/pwmgen.c


Lucky for me not many people use bzr, or you could easily see how stupid my 
bug was.  I think I'm safe from the humiliation until I commit it to the CVS 
tree later tonight...


-- 
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On the molecular scale, you find it's reasonable to have a machine
that does a million steps per second, a mechanical system that works at
computer speeds. -- K. Eric Drexler

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Re: [Emc-users] stepgen pwmgen fixes

2008-09-21 Thread Sebastian Kuzminsky
On Sunday 21 September 2008 16:04:48 Eric Johnson wrote:
 As for the PWM, I think I have something for you. It looks to me like
 something in the scaling must not be working in FPGA. Fortunately it does
 appear to be linear, so I think I can get my system going by adjusting my
 scaling. It may affect the granularity, but for this application that
 really isn't an issue.

 Here is what I am getting;

 Any value for the PWM set at 0.126 and above results in a duty cycle of
 almost 100% (99.3). At 0.125 the duty cycle is 99.1. The following table
 lists the duty cycles for values of 0.120 to 0.010 in increments of 0.010.

 ValueDuty Cycle
 0.120 95.3
 0.110 87.3
 0.100 79.5
 0.090 71.6
 0.080 63.7
 0.070 55.8
 0.060 47.9
 0.050 40.0
 0.040 32.1
 0.030 24.2
 0.020 16.3
 0.010  8.4

 Pretty consistent at 7.9% per 0.010 of value. As a hunch, it looks to me
 like you are off by 4 bits some place, because 0.125 is 1/8th of the range
 of 0.0 to 1.0.

How are you measuring duty cycle?

I'm confident that (at least in my test setup) setting pwmgen.XX.value causes 
the correct number to be set in the FPGA register.

Take a look at http://pastebin.ca/1208030.  I updated pwmgen.c to decode the 
number in the PWM Value Register, then used raw.dump-state to show the 
register when pwmgen.value was -1.0 to +0.3 in increments of 0.1.  Lines 1-22 
show the relevant dmesg output for .value=0, then I just show the PWM Value 
Register for the other .value settings.

In addition to the correct numbers being set in the register, the 
corresponding LED on the 7i31 LED Debug board varies in intensity as 
expected, and the small DC servo (driven by a 7i30 servo amp) changes its 
speed as expected.

I'm not sure why you're seeing what you're seeing.  Is maybe your pwmgen.scale 
not set to 1.0?


-- 
Sebastian Kuzminsky
On the molecular scale, you find it's reasonable to have a machine
that does a million steps per second, a mechanical system that works at
computer speeds. -- K. Eric Drexler

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