Re: gEDA-user: Zoom bug on Windows

2011-09-16 Thread Colin D Bennett
On Fri, 16 Sep 2011 21:23:50 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 DJ Delorie wrote:
 
  Try this snapshot:
  
  ftp://ftp.delorie.com/pub/geda-windows/snapshots/pcb-20110916.exe
 
 I tried in a virtual box with winXP. Now, I better understand
 Bobs problem. On the first call of the application, I got a
 dialog that asked which application to use for
 ListLibraryContents.sh. The windows noob in me guessed, that
 this is supposed to be the pcb binary. So I happily navigated to
 the snapshot dir and selected pcb. This was a terrible mistake. 
 Whenever I try to start PCB, it enters a loop and literally
 spawns more and more copies of PCB until all memory is used.
 These opies are not easy to kill, because they don't react fast
 enough. WinXP insists to ask wether it should sende a report to
 microoft for every single kill...
 
 Unfortunately, a remove and reinstall does not remove this
 problem. The faulty setting must resides somewhere in the windows
 configs. How I can get rid of them? And what should be the
 correct setting in the first place?

It sounds like 'bash' needs to be selected as the program to run
ListLibraryContents.sh, although I think pcb should explicitly
be calling a Bourne shell to run the script.  See src/main.c around
lines 1129-1130:

  SSET (LibraryContentsCommand, ListLibraryContents.sh '%p' '%f',
lib-contents-command, Command to query the contents of the library),

You should be able to delete or edit the file association Windows
made for *.sh files.  E.g., on Windows XP try
http://support.microsoft.com/kb/307859.  You can also use regedit
to manually edit the registry if you need to.

Regards,
Colin


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Re: gEDA-user: New gtk menu system

2011-09-16 Thread Colin D Bennett
On Fri, 16 Sep 2011 20:25:19 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 Kai-Martin Knaak wrote:
 
  See the attached screenshots
  how this theme renders mouse-over of route styles.
 
 Sigh. When will I ever learn to attach right with the original
 post... Here come the announced attchments. 

Hey, I know how you feel.  Maybe you need The AttachWarner plugin
for Claws Mail:
http://www.claws-mail.org/plugin.php?plugin=attachwarner

Regards,
Colin


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Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 10:12:26 +0100
BAXENDALE P.R. peter.baxend...@durham.ac.uk wrote:

 I've built a cygwin version of geda/gaf 1.6.2 and pcb and combined it,
 rather crudely, with the necessary cygwin bits to make it easy
 to install on a Windows PC. It's really intended for my students to use,
 but I've put it in http://www.dur.ac.uk/peter.baxendale/stuff/gEDA/ in
 case anybody finds it useful. It seems to work here, but hasn't been
 through the real test (the students) yet.

That's great!  How coincidental that I just opened up my mail
client to post to the list about how I could not find a Windows
build of gEDA!

I want to recommend gEDA to colleagues and online contacts, but
unless I can point them to a one-click Windows download, gEDA won't
be considered -- it'll surely be KiCad or (grimace) EAGLE.

Regards,
Colin


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Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 10:42:12 -0400
DJ Delorie d...@delorie.com wrote:

 
 I've built a cygwin version of geda/gaf 1.6.2 and pcb and
 combined it, rather crudely, with the necessary cygwin bits to
 make it easy to install on a Windows PC.
 
 Don't forget that you need to distribute the geda and cygwin sources
 with your binaries.  Yes, it's a pain, but yes, you have to do it.

How much of a pain is it to drop a couple of tarballs in the
downloads directory?  Especially when you can practically unlimited
disk space and monthly transfer bandwidth for only $10.00/month at
HostGator?

Regards,
Colin


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Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 10:44:21 -0400
DJ Delorie d...@delorie.com wrote:

 
  That's great!  How coincidental that I just opened up my mail
  client to post to the list about how I could not find a Windows
  build of gEDA!
  
  I want to recommend gEDA to colleagues and online contacts, but
  unless I can point them to a one-click Windows download, gEDA won't
  be considered -- it'll surely be KiCad or (grimace) EAGLE.
 
 You didn't notice my posting last week about my nightly
 geda-for-windows builds?  Or that a big part of the upcoming pcb
 release is a windows installer?
 
 Sigh.
 
 http://www.delorie.com/pcb/geda-windows/

Well, I wasn't looking for a Windows build at the moment when you
sent that message, and I don't have time to pay attention to every
message on every mailing list.

Yesterday, I needed to refer someone to a gEDA Windows installer,
so I went to (surprise!) the gEDA web site at gpleda.org.

 Note: this is mingw-based, not cygwin-based, and the installer exe
 only installs pcb at the moment (unzip the build-*.zip to get an
 everything install)

So is mingw-based better so the user doesn't have a huge cygwin
installation in their c:\cygwin?  It would be nice to have a more
self-contained install.  How much Unix tools does gEDA really need
to run?  Just the Scheme interpreter?  Is m4 required if you don't
use m4 footprint libraries?

Regards,
Colin


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Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 11:43:46 -0600
John Doty j...@noqsi.com wrote:

 On Sep 13, 2011, at 11:11 AM, Colin D Bennett wrote:
 
  How much Unix tools does gEDA really need
  to run?  Just the Scheme interpreter?

 Optional tools need a variety of support, e.g. Perl for refdes_renum, Python 
 for tragesym. To participate in gedasymbols.org, you need CVS, and
 some of the scripts there use AWK. Some design flows use Make. gEDA
 can export netlist data to many tools, but of course you'd need the
 tool in question to actually use this capability.

I'd like to allow a new user to be up and drawing schematics in a
few minutes.  New users shouldn't have to worry about details of
scripted symbol generation or netlist export until it is necessary.

All the more advanced pieces like Makefile-driven automation,
scripted symbol generation, netlist export, and so on are a
different story and that's fine if the user needs to install Python
or Perl or Cygwin to run some more advanced tools.

 gEDA is *not* a self-contained system. Hurray for that!

Sure! that's great since it shows that it can be further enhanced
with new scripts and tools, and your designs are not locked into
some secret file format.

Regards,
Colin


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Re: gEDA-user: reasons for wikibook (was: plugins)

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 21:24:57 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 Geoff Swan wrote:
 
  +1 I think it unlikely that a gEDA wiki would be targeted.
 
 It is very likely to be targeted by semi clever spam bots. I administrate 
 a couple of wikis. Plain, anonymous write accesss had to be disabled because
 they caught spam bots trying to distribute their spew after a few weeks. 
 Captchas work well for edits works as an antidot. But they are a hassle to 
 legitimate users, too.
 
 The only site I know, that manage to get away with open write access to 
 anyone and anything are those with a massive amount of users.

I see no problem with prohibiting anonymous edits.  It takes
only about 20 seconds to create a login, and you only have to do it
once.

Regards,
Colin


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Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Colin D Bennett
On Tue, 13 Sep 2011 20:36:25 +0100
BAXENDALE P.R. peter.baxend...@durham.ac.uk wrote:

  Don't forget that you need to distribute the geda and cygwin
  sources with your binaries.  Yes, it's a pain, but yes, you
  have to do it.
 
 The gEDA sources are in the zip, but I forgot about the cygwin
 ones. I'll take a look at how much time it would take to include
 them, otherwise I'll take it off the server again.

You don't have to put the sources in the same ZIP file as the
binary, do you?  You can provide a source archive in the same
download directory, right next to the binary download.  It would
probably be preferable both for you from a bandwidth standpoint and
for the users from a download time standpoint to provide sources in
a separate archive. Most users won't download the source.

Regards,
Colin


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Re: gEDA-user: CERN goes for KiCAD

2011-09-12 Thread Colin D Bennett
On Sun, 11 Sep 2011 13:16:23 +0200
Rubén Gómez Antolí l...@mucharuina.com wrote:

 Is something how Kde us Gnome?
 
 Because after of years of desktop wars, both proyects colaborate in base 
 (freedesktop) and expand his own style.
 
 There are something to learn in our own free software history?

That's a good point.  Where could things be best shared between
KiCad and gEDA?

While it would be nice to share a common schematic/PCB layout file
format, that seems difficult given the different approaches taken
by both tools.

My initial thought is that the biggest value-to-effort ratio would
be from being able realized by being able to share symbols and
footprints between the tools.  Of course even this has some serious
difficulties: consider all the special attributes and such required
for proper gschem symbols.  Perhaps gschem's format is detailed
enough that KiCad symbol information could be inferred from it.
Footprints might be simpler to share since there seem to be fewer
tool-specific details needed (just defining copper areas/pads,
pins/holes, solder mask and paste, silk screen lines).

Regards,
Colin


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gEDA-user: pcb “Optimize routed tracks” problems

2011-09-12 Thread Colin D Bennett
I've been trying to use the pcb track optimization tools on a board
which I've manually routed.  I tried essentially all the
options on the Connects | Optimize routed tracks menu.  However,
I've run into a couple of problems:

1. My board has an LQFP48 footprint rotated 45 degrees.
   Whenever I try to use the optimization tools, weird stairstep
   tracks appear on this IC's pads, shorting all of them together.

2. The optimization tools violated the DRC minimum spacing
   constraints.
   I removed the LQFP48 IC and instead put some circular “test pad”
   footprints in place of each of the IC's pads.  I was then able
   to get the optimization tools to sort-of-work.  However, the
   tracks were pulled too close to some other pins and it violated
   DRC minimum copper spacing.  Also, my tracks weren't very nicely
   pulled and optimized either.

Has anyone encountered these problems?
What is the status of the pcb track optimization features?
Do they perform better for automatically-routed tracks?
Are they useful only for very simple layouts?

Regards,
Colin


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Re: gEDA-user: pcb “Optimize routed tracks” problems

2011-09-12 Thread Colin D Bennett
On Mon, 12 Sep 2011 19:04:35 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Mon, Sep 12, 2011 at 02:38:20PM -0400, DJ Delorie wrote:
  
   1. My board has an LQFP48 footprint rotated 45 degrees.
  
  The ability to rotate parts happened after the optimizer work.  Any
  math majors want to take this one?
 
 
 I'm interested, but time-strapped. Can you give me a quick
 outline of what Optimize routed tracks is supposed to do
 and what source files it uses?

I looked back at DJ's page on the pcb trace puller
http://www.delorie.com/pcb/puller/ and realized that the
instructions there rely on using arcs in the tracks.  Perhaps a
sequence of lines is not pulled properly?

My goal was to do some rough, but not pretty (nor tightly spaced)
routing of traces, then use the puller to pull all my parallel
traces nice and tightly together as they bend around other parts,
and to eliminate all the “jaggies” as they stairstep down together
in certain cases.

Anyway, it sounds like in their current state, the
Optimize Tracks tools are not really usable for manually routed
boards.  If they would at least adhere to DRC constraints, that
would make them more of an option.  (Note that my initial traces
before running the optimizer did pass DRC with no errors.)

Regards,
Colin


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Re: gEDA-user: why some skip KiCAD and gEDA

2011-09-08 Thread Colin D Bennett
On Thu, 08 Sep 2011 17:50:33 +0200
Stefan Salewski m...@ssalewski.de wrote:

 For me, I never loved the many tool changes, and I was never able to
 remember all the key combinations. er is edit rotate, ve is view
 extend. For the later I am not really sure -- have not used gschem for a
 year.

Don't forget, while “ve” is View Extents, “ev” alters all invisible
text and attributes making them visible!

It is not like “en” which just toggles the display mode to show
invisible text, but “ev” actually changes the entities.  If you
don't realize what happened and undo it right away, you will
basically screw up the whole schematic.  (I think “ev” action
should be removed or at least prompt for confirmation; I've said so
before on this list.)

Regards,
Colin


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Re: gEDA-user: time for a pcb release cycle?

2011-09-07 Thread Colin D Bennett
On Wed, 07 Sep 2011 12:54:27 +0100
Peter Clifton pc...@cam.ac.uk wrote:

 On Wed, 2011-09-07 at 10:42 +0200, Kovacs Levente wrote:
  Each time I save my layout, a message appears: layout changed. Do you
  want to load it? or something like that.
  
  Brr well of couse it changed! I saved it! :-) Ok, I know it is a 
  good
  feature...
 
 Yes - it turns out that my code here is very buggy. I'm working on a
 fix, but it turns out that there are some quite subtle things going on. 
 
 Disconnecting the file-watch before save, then re-connecting it after
 doesn't even work (sometimes), as for some reason - after having used
 the GTK file-selector dialog to pick a file-name, the file-watch code
 will report events from changes on disk BEFORE you hooked it up.

How about this for a solution:

1. When saving to disk, don't disconnect/reconnect the file watch,
   just leave it connected.  However, ignore any file modification
   events until the save is completed.
   Set a flag: ignore_changes := True

2. Immediately after the save is completed, read the modification
   time on the file from disk.  Store this time:
   save_time := file.mtime

3. Set ignore_changes := False to resume processing file
   modification events.  The modification event handler should,
   however, ignore any modification event if the file modification
   time is equal to the previously captured save_time.

Regards,
Colin


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Re: gEDA-user: Strange user interface behavior with gschem-1.6.2.20110115

2011-09-07 Thread Colin D Bennett
On Wed, 7 Sep 2011 19:12:03 +0200
Josef Wolf j...@raven.inka.de wrote:

 On Tue, Sep 06, 2011 at 11:27:08AM -0700, Colin D Bennett wrote:
  I have recently started to like the gschem Magnetic Net mode, now that
  I learned to use Ctrl-click to put explicit intermediate points in the
  lines instead of just clicking the two endpoints and letting gschem
  route the line.
  
  But this annoying problem you have encountered, where clicking causes
  the line to connect SOMEWHERE OTHER THAN WHERE THE CIRCLE WAS SHOWN is
  extremely irritating.  To reduce the impact of this issue, you
  can manually place a number or intermediate points so that the final
  “magnetic” action to the target pin has a shorter distance to go.
 
 With this work flow, you'd have as much (or even more) mouse clicks as
 without the tool. So what's the point of using the tool if you have _more_
 work with it than without it?

Well, I would really have the same number of mouse clicks in the
worst case, but the only benefit from magnetic mode is on the last
click, where you can use Magnetic Net mode to overcome Fitts's law
and not have to click *exactly* on the tip of that tiny pin,
especially when you are zoomed out really far to route that net.

Ideally, I would the opposite of the current mode: to turn off
Magnetic Net mode by default but be able to opt-in for a single
click by holding down Ctrl while clicking.

Regards,
Colin


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Re: gEDA-user: Strange user interface behavior with gschem-1.6.2.20110115

2011-09-06 Thread Colin D Bennett
On Tue, 6 Sep 2011 12:59:39 +0200
Josef Wolf j...@raven.inka.de wrote:

 On Mon, Sep 05, 2011 at 09:13:06PM +0200, Kai-Martin Knaak wrote:
   IMHO, this works against user expectation. After all, the whole
   point of the circle is to signal the user where the connection
   would be done. Connecting to anything other is not exactly what
   the user would expect. 
   From the perspective of the user it is totally irrelevant
   what algorithm is used internally.
  
  But it is relevant to know, what this mode is intended for --
  magnetic- mode, not auto-complete. I am sure, you got the point
  now :-)
 
 I don't care how it is called as long as it connects to the wrong
 destination. Oh, I already wrote this above ;-)

+1
I have recently started to like the gschem Magnetic Net mode, now that
I learned to use Ctrl-click to put explicit intermediate points in the
lines instead of just clicking the two endpoints and letting gschem
route the line.

But this annoying problem you have encountered, where clicking causes
the line to connect SOMEWHERE OTHER THAN WHERE THE CIRCLE WAS SHOWN is
extremely irritating.  To reduce the impact of this issue, you
can manually place a number or intermediate points so that the final
“magnetic” action to the target pin has a shorter distance to go.

Regards,
Colin


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Re: gEDA-user: pcb gtk: Toggle buttons for route styles?

2011-09-02 Thread Colin D Bennett
On Thu, 1 Sep 2011 10:55:10 -0700
Andrew Poelstra as...@sfu.ca wrote:

 Can we use toggle buttons instead of radio buttons for the
 route style selector? It would look like so:
 
 http://wpsoftware.net/andrew/dump/toggle.png
 
 This gives more clickable area and a cleaner look, I think.

While we're thinking about the route style buttons, I this it would be
ideal to:

- Use toggle buttons as you suggest,

- Remove the “Route Style” button, and

- Put either a small “edit” icon next to each route style name, 
  or maybe more consistent with the new layer selector,
  allow right-click on name to edit (I often want to quickly look at
  the settings for a different route style without having to change
  to it, click Route Style, then change back to the previous route
  style.)

Regards,
Colin


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Re: gEDA-user: pcb gtk: Toggle buttons for route styles?

2011-09-02 Thread Colin D Bennett
On Fri, 2 Sep 2011 09:46:02 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Fri, Sep 02, 2011 at 03:02:51AM +0200, Kai-Martin Knaak wrote:
  Andrew Poelstra wrote:
  
   Can we use toggle buttons instead of radio buttons for the
   route style selector? It would look like so:
   
   http://wpsoftware.net/andrew/dump/toggle.png
   
   This gives more clickable area and a cleaner look, I think.
  
  The look is still inconsistent. The buttons are centered. By
  contrast, the tool box and the layer lines are flush-left.
  
  
  I'd prefer a more radical change:
  
  1) Make the route styles as user configurable as the layers. That
  is, allow to add odr delete styles, change the order they appear 
  in the GUI, 
 
 
 Nope, core changes required. I can allow the addition of arbitrarily
 many temporary layers (and I plan to), but that's pretty much the
 extent of what I can do without making serious changes.
  
  2) Attach accel-keys to route styles. I know, we are running out 
  of accels. But this is an important omission in the current GUI. 
  Changing route styles is a very frequent action while manual 
  routing. How about [ctrl-F1], ... [ctrl-F12]?
 
 
 Sure. Unless someone has a better idea, I'll go with these.
  
  3) Add a little preview to the left of the route style name, that
  indicates the width of the tracks. Actual width in the preview may 
  be calculated relative to the other route styles. 
  
 
 I considered this, but route styles control more than just line
 size, and I don't think relative to the other route styles would
 be very useful.
 
  4) Get rid of the Route Style button. Its meaning depends on
  the currently selected route style. This is very non-standard and 
  newbie unfriendly. 
 
 Here is my proposal: add an 's' to Route Style and have it load
 this dialog:
 
 http://wpsoftware.net/andrew/dump/styles-dialog.png

How about a dialog that presents all the route styles in a table, so
they can be easily compared?  It is difficult to compare two styles
(say, to make sure the via size is the same for two styles, or
something) when you can't see both at once.

  Proposal: Move its function to right-mouse click on every style
  button. Ideally, this would be complimented by a config page in
  prefernces in case a user can't do right-clicks (e.g. mac users).
  This would also be the place to change order config accel keys or
  add more route styles. Side effect: More space in the right
  sidebar :-)

+1
I would like right-click to bring up properties for any route style
*without* having to make it the current route style (sometimes I want
to quickly check the settings for a particular style.



Regards,
Colin


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Re: gEDA-user: Fwd: Re: [OH Updates] How can you help solve the proprietary tool problem?

2011-09-02 Thread Colin D Bennett
On Fri, 02 Sep 2011 10:18:20 -0500
John Griessen j...@ecosensory.com wrote:

 Does the category low end bother you?

Well, I think low-end is not very specific in reality.  Does gEDA
really belong in the category of EAGLE, or is it much more powerful?

Maybe the “low-end” attitude toward gEDA is based on the fact that pcb
doesn't support important features for large and complex boards such as

- trace length matching,
- constraints/routing styles defined at the net level,
- pushing/pulling PCB traces and better support for moving parts with
  traces routed,
- ability to select a component on the PCB by clicking it in the
  schematic view,
- back-annotation to schematic from the PCB editor.

Just a few things that sound important to me, a novice PCB designer.

Regards,
Colin


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Re: gEDA-user: New gtk menu system

2011-08-31 Thread Colin D Bennett
On Tue, 30 Aug 2011 14:22:28 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Tue, Aug 30, 2011 at 06:51:10PM +0200, Kai-Martin Knaak wrote:
  
  Some glitches:
  I don't see any visual feedback which item the mouse cursor
  currently refers to. Gnome user expectation seems to be, that the
  item should be highlighted with background changing to focus color.
  Much the same way that the items in a menu highlight on mouse-over.
  Currently, I get focus color only after I clicked a layer.
 
 
 
 Here is some visual feedback. It brightens the swatches when
 the mouse is over the row, a little bit. Let me know what you
 think of it.

I didn't try it yet, but will it work for layers with the following
colors:

- white layers (e.g., silk) or black layers?

- layers with colors like red, green, blue, yellow, cyan, etc. where
  all of R,G,B are either 0.0 or 1.0 (normalized scale)?

A more general solution, and one that won't affect the accurate
representation of the layer color by the swatch, is to draw a 1 or 2
pixel wide border around the swatch when the mouse hovers over that
layer button.

Regards,
Colin


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Re: gEDA-user: Tearoffs on popup menu in pcb?

2011-08-30 Thread Colin D Bennett
On Mon, 29 Aug 2011 19:36:21 -0400
DJ Delorie d...@delorie.com wrote:

 I don't think it makes sense for a popup to be tear-off-able, since
 popups are supposed to be context sensitive, and if you tear it off
 you lose context.
 
 I.e. if you right-click on an element, you should get a menu specific
 to that element, like select to select *that* element, rotate to
 rotate *that* element, etc.  Such an operation makes no sense if the
 popup is torn off and placed elsewhere.

Good point!

Regards,
Colin


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Re: gEDA-user: gschem: Modifier keys for moving?

2011-08-30 Thread Colin D Bennett
On Tue, 30 Aug 2011 01:03:05 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Colin D Bennett wrote:
 
  Are you running an old version of GTK?
 
 My distro is debian/testing, aka squeeze. The libgtk2 packages are
 mostly version 2.24.4-3 . Is this old? 

No, not old.  I have the same 2.24.4 version (Ubuntu
11.04 libgtk2.0-0 package version 2.24.4-0ubuntu2).
Perhaps the Debian verson has some special patches applied to resurrect
the tear-off feature?  I would expect the same patches to be in Ubuntu,
however.

Regards,
Colin


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Re: gEDA-user: gschem: Modifier keys for moving?

2011-08-29 Thread Colin D Bennett
On Fri, 26 Aug 2011 19:30:02 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Abhijit Kshirsagar wrote:
 
  Actually, with respect to the rubber-band mode (both in PCB and
  gschem, as a matter of fact) I have no clue whether the mode is
  'on' or 'off'. I can only test the behaviour by doing something
  and/or toggling from the menu.
  
  Am I missing something here or is this normal?
 
 In PCB I habitually rip off the settings menu and put it somewhere
 right of the canvas. This menu shows checkmarks for active options.

Are you running an old version of GTK?  My pcb tear-off menus are
completely nonfunctional -- clicking menu items on the torn-off menu
does not toggle the checkmark, for instance.

Regards,
Colin


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Re: gEDA-user: Tearoffs on popup menu in pcb?

2011-08-29 Thread Colin D Bennett
On Sun, 28 Aug 2011 20:38:27 -0700
Andrew Poelstra as...@sfu.ca wrote:

 Right now in pcb if you shift-right-click on the main viewport,
 you get a popup menu with a few submenus. There are no tearoffs.
 
 Do you want tearoffs on the submenus of this popup?
 
 What about on the popup itself?

Am I missing something?  The tear-off menus do not work for me anymore.
I'm running Ubuntu 11.04.

Regards,
Colin


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Re: gEDA-user: gschem vs. PCB diode pin numbering

2011-08-29 Thread Colin D Bennett
On Fri, 26 Aug 2011 11:34:04 +0200
Kovacs Levente leventel...@gmail.com wrote:

 When you use a light symbol, a script finds a pinmap, and constructs
 a heavy symbol. Say for example if you have a SOT23 diode with A1A2K
 pinout you'll get a symbol with name like 'diode-SOT23-A1A2K.sym'
 this symbol is then copied to the project's symbol directory, and the
 original symbol name in the schematic is replaced by the name of the
 newly created symbol. The script will add other information as well
 like footprint name, etc.
 
 With this, you don't have to mess with your symbols nor with your
 footprints, and everything works quite well for me.
 
 Of course, everything is makefile driven... etc. The pinmap and
 symbol names are coming from a database.

Nice!  That sounds very slick.  Have you shared your code for this
pin-mapping tool?

Regards,
Colin


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Re: gEDA-user: essential library -- plaese comment.

2011-08-29 Thread Colin D Bennett
On Mon, 29 Aug 2011 03:23:09 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 This of course implies heavy symbols. In fact, I made them super
 heavy by adding an attribute with a comma separated list of
 footprints. So dear light library lovers: This is explicitly not for
 you ;-)

First, I'll say that I am an advocate of lightweight symbols, and I
want to draw my schematic once, not having to delete and re-add symbols
when I decide to change a resistor from 0805 to 0603 footprint; or when
I change a 2 row, 6 contact connector to a single-row 6-contact
connector; or most significantly when I change a SOT-23 (3-lead SMT)
transistor to a 4-lead package including a tab; etc.

That being said...  I wouldn't say your method is “super heavy” but
rather it is “flexibly heavy”.

I see your idea of having not just one footprint in the symbol, but
multiple options for a footprint as an *improvement* to the current
heavyweight symbols, which only provide a single footprint option.  (Of
course advanced users can just edit the symbol instance in the
schematic and change the footprint, but then you might as well have
used lightweight symbols in the first place.)  If gschem could present
the user with the list of possible footprints, then this would be a
decent way for new users to get started and would give good flexibility
too.

Regards,
Colin


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Re: gEDA-user: How to do PCB Autorouting with non-plated holes

2011-08-25 Thread Colin D Bennett
On Wed, 24 Aug 2011 16:33:05 -0400 (EDT)
Cory Papenfuss papenf...@juneau.me.vt.edu wrote:

   Thanks for all the suggestions.  I've played with it a bit
 and come up with an example for a 200mil radial capacitor below:
 
 Element[  C0  97000 208000 8000 -28000 0 100 ]
 (
  Pin[0 0 0 3000 6600 3000  1 hole,square]
  Pin[2 0 0 3000 6600 3000  2 hole]
  Pad[0 0 100 0 6000 3000 9000  1 onsolder,square]
  Pad[2 0 20100 0 6000 3000 9000  2 onsolder,edge2]
  ElementArc [1 0 2 2 0 360 1000]
 
  )
 
   I have never had to muck with footprints manually, so it's a
 bit of a learning curve for me.  The footprint Colin provided doesn't
 have a solder mask that's quite right (Resistor_TH_FarPads.fp).  It
 appears that in order to fix is, I had to add the square flag to
 the Pin as well as to the Pad.

At first glance, it may look like the solder mask is wrong, but in fact
if you hit Tab to view from the back side of the board and enable
solder mask view, you will see it is correct.

Alternatively, look at the front side of the board and disable the
“far side” layer.  Enable the solder mask layer.  Observe that the
solder mask on the top layer actually has a round hole for the pin.

The solder mask on the front side of the board has a round opening, to
leave space around the hole.  The solder mask on the back side has a
square hole for pin 1's “Pad”.  Viewing the board from the front
doesn't show the difference by default.

Regards,
Colin


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Re: gEDA-user: gschem vs. PCB diode pin numbering - anode/cathode definition

2011-08-25 Thread Colin D Bennett
On Thu, 25 Aug 2011 08:28:46 -0400
Ethan Swint eswint.r...@verizon.net wrote:

 On 08/24/2011 01:15 PM, Colin D Bennett wrote:
  I understand that it is electrical convention to name diode terminal
  anode and cathode, but I reject it as a confusing and ambiguous
  naming convention.
 Yes, it's not quite correct, but it is a widely held convention,
 unlike numbering the pins 1 and 2 (or 3 or 4).

Agreed that A and K certainly avoids ambiguity, as compared to
numbering diode pins simply 1 and 2.  It is 100% superior as it does
convey the required information.

  For my diode symbols and footprints, I choose to name the terminals
  “P” and “N“ (for the p-type doped side and the n-type doped side).
 If you use P and N, Schottky diodes are now in error.  ;)

Good point.  The moral of the story is: at least name the pins in a
way that communicates the pin's function in a clear way.  I will have
to make my peace with the fact that there is no 100% technically
correct way to do so... at least we can avoid errors caused by
arbitrarily naming pins 1 and 2.

Regards,
Colin


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Re: gEDA-user: gschem vs. PCB diode pin numbering

2011-08-25 Thread Colin D Bennett
On Thu, 25 Aug 2011 22:41:28 +0200
Levente Kovacs leventel...@gmail.com wrote:

 On Thu, 25 Aug 2011 14:03:35 +0200
 Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:
 
  Why not?
 
 Pinnumbers are numbers in the first place. Former versions of
 netlisters/PCB got confused by non-digital pinnumbers.

Who cares?  There's no reason to restrict ourselves from doing it right
when the tools support it now.

 With this approach you have to have a SOT23 footprint with 1,2,3
 pinout, A,K,NC pinout, A1,A2,K pinout, B,C,E pinout etc. Sooner or
 later, your library will contain duplicated data. What if you
 discover that you want to modify the shape of the SOT23.fp footprint?
 You have to modify all of them. Yuk.

I won't get into it too much here; the logical vs. physical pinnumber
assignment has been discussed in much detail before.
http://thread.gmane.org/gmane.comp.cad.geda.user/32149/focus=37188

 I think a footprint must have only *one* pinout, that is a standard
 pinout of the package. Have an intermediate layer (scripts, database,
 pinmaps, etc.) that do the heavy lifting for you.

Maybe in an ideal world (when pin mapping orthogonal to the schematic
and layout is introduced), but for now, the only two ways to handle
transistors etc. properly is to either

(1) create separate symbols for each pinout, where pinnumber is
assigned numerically according to package pin number (1, 2, 3).
For instance, you would need symbols NPN-EBC, NPN-BCE, etc., and
potentially different symbols for packages with a fourth “tab” pin such
as SOT-223-4 http://www.onsemi.com/pub/Collateral/NSS40300MZ4.PDF; or

(2) create separate footprints for each pinout, using logical
pinnumbers B, C, E, and footprints that assign these to appropriate
package pins; then you only need two BJT symbols “NPN.sym” and
“PNP.sym” that use these logical pins; this supports packages with a
fourth “tab” pin without cluttering the schematic, and allows such
details as pinout to be deferred until after basic schematic drawing.

Do you really want to delete and re-add each of your dozens of
transistors in gschem when you change the transistor to one with a
different pinout?  If you use a logically-pinned symbol, you can easily
change the pinout by just editing the footprint attributes (gattrib,
gschem property editor, export/import to/from spreadsheet, etc.).

Conversation regarding TO-92 transistor package pinouts:
http://thread.gmane.org/gmane.comp.cad.geda.user/37190/focus=37197

Well, I always say I won't get into the logical/physical pinning
debate, but I always do. :-)  For me, using logical pins on the
schematic symbols such as transistors and diodes (*especially* diodes in
IC packages like SOT-23) is the only way that makes sense ... at least
until proper pin mapping is implemented.

Regards,
Colin


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Re: gEDA-user: howto pin size

2011-08-24 Thread Colin D Bennett
On Wed, 24 Aug 2011 14:14:23 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Wed, Aug 24, 2011 at 05:14:43AM -0500, kqt4a...@comcast.net wrote:
  I have a component with a pin that info shows copper width = 72
  I want to set copper width to 70 so I go to
  File-Preferneces-Increments and set Size Increment/Decrement to 1
  and press OK
  Now put cursor over pin and press shift-s
  Info shows copper width = 67
  How do I increment/decrement size by smaller values
 
 Richard, the Increments tab is completely non-functional right now.

Should it be hidden, or “grayed out” by disabling its widgets until it
is fixed?  Let's try not to confuse users.

 If you would like to change copper width, click on the Route Style
 button on the bottom-left of pcb, and manually enter the new
 width.

That won't change the pin on his component, however, will it?
I think he needs to select the component pin, and then type
“:ChangeSize(Selected, 70mil)” and press Enter.

Regards,
Colin


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Re: gEDA-user: gschem vs. PCB diode pin numbering - anode/cathode definition

2011-08-24 Thread Colin D Bennett
On Wed, 24 Aug 2011 08:21:17 -0400
Ethan Swint eswint.r...@verizon.net wrote:

 On 08/23/2011 08:47 PM, Matthew Lewis wrote:
  I was double checking a pcb layout today and I discovered a rather 
  nasty gotcha. It seems that gschem and PCB don't agree on which end
  of a diode should be pin 1. Gschem views pin 1 as the anode and PCB 
  considers pin 1 to be the cathode. It doesn't prevent you from
  laying out a board correctly, but it does cause the silkscreen
  polarity to be printed backwards (for the SOD devices at least).

 I've defined my own symbols and footprints to use 'A' and 'K' instead
 of 1 and 2.

That's a good idea.  Anything you can do to error-proof yourself is
a Good Thing.

However, I refuse to use “anode” and “cathode” for diode symbols, since
these terms refer to electron flow and are _incorrect_ when the diode is
reverse-biased (most obvious for common Zener diode circuits).

I understand that it is electrical convention to name diode terminal
anode and cathode, but I reject it as a confusing and ambiguous naming
convention.

For my diode symbols and footprints, I choose to name the terminals
“P” and “N“ (for the p-type doped side and the n-type doped side).
This models the structure of the device in an unambiguous way.  This
works perfectly for all types of diode (including LEDs), no matter how
the device is used in the circuit.

John Denker describes the most obvious problem with anode/cathode
for Zener diodes [1]:

You should never apply the terms anode or cathode to a Zener
diode, because the potential for confusion is too great.
Instead you should refer to the P-doped side and the N-doped
side, and you should insist that others do the same.

Note that reversing the labeling convention for Zener diode
arrays would not solve the problem in any fundamental sense,
because there are perfectly reasonable circuits in which –
part of the time – a Zener diode is forward biased, so that
it conducts just like any other diode. This is the same
situation we encounter in connection with rechargeable
batteries: if you attach permanent anode/cathode labels to
the structure, you will be wrong at least part of the time.

The terms “anode” and “cathode” properly apply to function,
not structure.

Rechargeable batteries are another place where the terms anode and
cathode can cause confusion due to the fact that current can flow
either direction between the battery terminals [2].  User PaulW had an
interesting insight in comment #8 regarding the fact that “anode” and
“cathode” are important from a battery chemistry standpoint, but
“positive” and “negative” terminals are more useful from an electric
perspective.

Regards,
Colin

REFERENCES


[1] John Denker. “How to Define Anode and Cathode.”
http://www.av8n.com/physics/anode-cathode.htm#i-zener.

[2] candlepowerforums.com thread started by Clifton Arnold.
“anode is it positive or negetive” (sic).

http://www.candlepowerforums.com/vb/showthread.php?41548-anode-is-it-positive-or-negetivep=453381viewfull=1#post453381.



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Re: gEDA-user: How to do PCB Autorouting with non-plated holes

2011-08-24 Thread Colin D Bennett
On Tue, 23 Aug 2011 22:53:23 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Cory Papenfuss wrote:
 
  I thought about that... making different footprints that don't 
  have copper on the component side of the pins.  Since that would
  require making new footprints for pretty much everything,
 
 Well, you could do the heavy lifting with an awk script: 
 
  If the current line is a pin,
 set the diameter of the pin to zero and add a hole flag
 ouput a round pad with the diameter of the pins annular ring
  else, 
 output the current line unchanged.   

Could you do this on the layout (.pcb file) after all elements are
placed so he would not even need to create new footprint files?

  I was hoping for a 
  different solution... :)  It seems like it would be a relatively
  common thing for hobbyists to want (whether it's a milled or
  home-etched board), so I thought there might be a setting on the
  autorouter config to ignore component hold plating or something.
 
 IMHO, the copperless pin solution is superior. It models the layout
 like it is in reality.

Besides the autorouter, I have made the same errors with manual routing
on self-fabricated double-sided printed circuit boards, which did not
have plated through-holes, so that is a significant and practical
reason that modeling the board as it is in reality is ideal (rather
than only fooling with the autorouter).

Regards,
Colin


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Re: gEDA-user: Foss-pcb Proposed plan from CERN

2011-08-24 Thread Colin D Bennett
On Wed, 24 Aug 2011 08:42:26 +0100
Peter Clifton pc...@cam.ac.uk wrote:

 For converting legacy designs, an import from gerber might be more
 generally useful to our user base, and doesn't require decyphering
 unknown file formats. Admittedly this looses footprint information,
 but perhaps that isn't always an issue.

Also, a gerber import feature for pcb would be generally useful for
other purposes in addition to supporting Altium import.  It would of
course support import from any other PCB layout package.  It could also
be used for panelizing boards given a bunch of boards each as a set of
gerbers. (I'm thinking along the lines of Laen's DorkbotPDX PCB order.)

Regards,
Colin


signature.asc
Description: PGP signature


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Re: gEDA-user: Layer button backgrounds - summary

2011-08-23 Thread Colin D Bennett
On Tue, 23 Aug 2011 10:36:33 +1000
Stephen Ecob silicon.on.inspirat...@gmail.com wrote:

 A few hours in the future, Andrew Poelstra as...@sfu.ca wrote:
  On Tue, Aug 23, 2011 at 09:52:19AM +1000, Stephen Ecob wrote:
  A few hours in the future, Andrew Poelstra as...@sfu.ca wrote:
  * Hide all layers button
 
  * Show all layers button
 
  These would be easy enough to add to the widget. Just tack an
  `All Layers' entry below the other non-selectable entries.
 
  Whether there would be demand for this, I don't know. Would it
  affect the pins, pads and via layers? Would it affect the solder
  mask layer? Why would you want to hide everything?
 
 Often I want to see one layer alone, so it would be convenient to be
 able to hide all and then show a single layer, using just 2 clicks.
 In your example artwork there are 14 layers, going from all visible to
 just one visible would take 13 clicks.
 
 When I'm finished checking that single layer I generally want to go
 back to all layers visible, so another 13 clicks!  That's why I'd like
 a show all button.

In the GIMP, you can Shift-click the visibility toggle “eye” button to
make only that layer selected (hiding all others) and Shift-click again
to make all layers selected.  I propose we implement this same feature.

Question: Which layers would be hidden when a copper layer is made
“solo-visibile” by being Shift-clicked?  Usually you want silk,
pins/pads, vias, etc. to still show but only hide all other copper
layers.

Regards,
Colin


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Re: gEDA-user: pcb HID GUI options: gtk, lesstif?

2011-08-23 Thread Colin D Bennett
On Mon, 22 Aug 2011 20:58:27 -0400
DJ Delorie d...@delorie.com wrote:

 
  if you use pcb with the Lesstif GUI, why?
 
 The lesstif GUI was designed to use very little screen space, leaving
 the maximum amount of space for the board.

I just tried out the lesstif pcb GUI.  I was surprised to see that
there is no tool palette or layer list at all; you must use the menus
to select tool, active layer, or shown/hidden layers.  (Except some
keyboard accelerators.)  I thought I saw screenshots of the lesstif GUI
where there *were* layer and tool bars on the left side of the window.
Am I mistaken?

I do like the huge space the lesstif GUI gave me for my board!  My
screen actually seemed to become physically larger. 

It would be great if the gtk GUI could provide some options to increase
available screen space -- perhaps a command to show/hide the left-side
tool and layer palette bar, and even an auto-hide feature that would
show the tool/layer bar only when the mouse moved to the left side of
the screen.  I look forward to Andrew Poelstra's new layer list GTK GUI
update, and hope the wasted horizontal 50 px or so around the current
layer widgets can be eliminated.

 It also serves as a check point to make sure the HID interface doesn't
 become gtk-specific.  Peter and I seem to be taking the two GUIs in
 different directions, which helps make sure that we *can* continue to
 do such things.

Nice.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds - summary

2011-08-23 Thread Colin D Bennett
On Tue, 23 Aug 2011 02:41:53 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Tue, Aug 23, 2011 at 02:22:25AM +0200, Kai-Martin Knaak wrote:
  Andrew Poelstra wrote:
  
   I have implemented the italicized/separated
   suggestion. You can see it here:
   
   http://www.wpsoftware.net/andrew/dump/mockup4.png
  
  Nice. 
  I note, that the longest layer name is solder mask. Why not
  shorten it to mask to save screen estate for the canvas?
 
 
 I'd be cool with this, but solder mask is a well-known phrase
 in the industry. It has a definition on Google and a Wikipedia
 page.
 
 mask has nowhere near the same information content. IMHO, it
 is not worth the space savings. Maybe s.mask would be better?

Perhaps it would be best to make the displayed name of the solder mask
layer a user preference.  Also, it would be nice to give the user
control over the layer name font size:  then a user could choose a
small font.  My general system font is too big for use in pcb, where I
really want maximum screen real estate available for the board.  I
found the lesstif GUI uses more reasonable (i.e., smaller) font
sizes on my Ubuntu system.

Regards,
Colin


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Re: gEDA-user: How to do PCB Autorouting with non-plated holes

2011-08-23 Thread Colin D Bennett
On Tue, 23 Aug 2011 07:15:54 -0400 (EDT)
Cory Papenfuss papenf...@juneau.me.vt.edu wrote:

   Hey, all.  I've used PCB on an off for 10 years and recently
 have been getting familiar again with the rest of gEDA which has
 become a great set of tools!
 
   Anyway, I've been using a board mill to make 1 and 2-layer 
 prototypes of typically through-hole components.  The trouble is when
 the autorouter chooses to use a component pin as a via to transition
 to the other layer.  If it's a part that doesn't have room to solder
 the topside (most parts... DIPs, ribbon-cable connectors,
 can-electrolytic caps, etc), it's very difficult to connect both
 sides.
 
   I typically check manually, but it's tedious and I often
 miss some.  Is there any way to set up the autorouter to ignore
 component-layer pads, but still route on the component layer
 elsewhere?  I've scoured the web for ideas but come up only with
 kludging a no-autoroute-zone by placing copper on the component
 layer before autorouting.

Since you have no plated holes, the component footprints are really
incorrect.  Through-hole footprints generally specify plated holes for
all pins.  However, I think this does not need to be the case.  I've
had similar problems with manual routing, when I accidentally route
traces to through-hole pins on non-plated-through-hole boards which
necessarily be soldered on that side.

Here is an idea of how you could use a footprint that specifies that a
copper annulus exists on the far side of the board only.  Instead of a
plated pin, it includes a pure hole and an SMT pad on the far side.
You can test it and see if it does what you want.  You could also put a
pad on the component side too, if you were going to solder the leads
there as well, and thus create a via with the component lead.

See attached footprint file.

Regards,
Colin


Resistor_TH_FarPads.fp
Description: application/pcb-footprint


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Re: gEDA-user: pcb HID GUI options: gtk, lesstif?

2011-08-23 Thread Colin D Bennett
On Tue, 23 Aug 2011 14:29:50 -0400
DJ Delorie d...@delorie.com wrote:

 
  That would play nice on a dual headed setup.
 
 One of my dream projects is to do a GUI for pcb that uses two or
 more monitors, with one monitor heavy on the toolbars and showing an
 overview thumber window, and the other monitor being 100% layout.

Split or multiple-view support was one of the requested features in the
Foss-pcb list linked to by the current geda-user “Foss-pcb Proposed plan
from CERN” thread.

It seems that if pcb is designed using best-practice
model-view-controller design, then multiple views should be simple.
I know that it's never that easy, though, since even when you do try to
implement a model-view-controller design, when you have only a single
view it is easy to take shortcuts and use global state, etc., so there
are usually things to iron out.

  There were fights against GTK people not to take tear-off menus from
  gtk3. But they did AFAIK.
 
 The lesstif tear-off model isn't so hot either.  I've been considering
 writing my own from scratch to work around some of the weirdisms.

I used the tear-offs for grid size when it worked, so I could quickly
switch back and forth between fine and coarse, imperial and metric grids
while working.

A more ideal solution than tear-off menus is a customized non-modal
dialog, window, or dockable toolbar of some sort that provides better
control for specific features.  For instance, instead of the predefined
grid items on the Grid Size submenu, it could have the user-defined
grids (see “new grids for pcb” feature that I REALLY WANT TO SEE) and
it could use better widgets rather than being stuck with a linear list
of menu items.

Regards,
Colin


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Re: gEDA-user: pcb segmentation fault

2011-08-22 Thread Colin D Bennett
On Sun, 21 Aug 2011 07:33:36 -0500 (CDT)
kqt4a...@comcast.net wrote:

 I am using version 1.99z that I compiled a few days ago
 If I press control-r while the mouse is over a component name I get a
 segmentation fault

I have seen this recently too.  I can't reproduce it exactly right now,
but I do get weird garbage characters in the Report window that does
pop up.  Running with Valgrind gives a very long stream of these traces
sometimes, but it depends on which component name I hover over:

==20085== Use of uninitialised value of size 8
==20085==at 0x6E68010: ??? (in 
/usr/lib/x86_64-linux-gnu/libpangoft2-1.0.so.0.2800.4)
==20085==by 0x12B71219: ??? (in 
/usr/lib/x86_64-linux-gnu/pango/1.6.0/modules/pango-basic-fc.so)
==20085==by 0x77A54A9: pango_shape (in 
/usr/lib/x86_64-linux-gnu/libpango-1.0.so.0.2800.4)
==20085==by 0x779891D: ??? (in 
/usr/lib/x86_64-linux-gnu/libpango-1.0.so.0.2800.4)
==20085==by 0x779928E: ??? (in 
/usr/lib/x86_64-linux-gnu/libpango-1.0.so.0.2800.4)
==20085==by 0x779B4C4: ??? (in 
/usr/lib/x86_64-linux-gnu/libpango-1.0.so.0.2800.4)
==20085==by 0x779C355: ??? (in 
/usr/lib/x86_64-linux-gnu/libpango-1.0.so.0.2800.4)
==20085==by 0x614C126: ??? (in /usr/lib/libgtk-x11-2.0.so.0.2400.4)
==20085==by 0x7EA2764: g_closure_invoke (in 
/usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0.2800.6)
==20085==by 0x7EB37E2: ??? (in 
/usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0.2800.6)
==20085==by 0x7EBD257: g_signal_emit_valist (in 
/usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0.2800.6)
==20085==by 0x7EBD60C: g_signal_emit_by_name (in 
/usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0.2800.6)
==20085== 


Regards,
Colin


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Re: gEDA-user: Preventing elements from appearing in BOM

2011-08-22 Thread Colin D Bennett
On Mon, 22 Aug 2011 08:09:03 -0400
Ethan Swint eswint.r...@verizon.net wrote:

 On 08/20/2011 11:50 AM, Matthew Lewis wrote:
  Is there a way to prevent a device from appearing in the BOM and in 
  the XYRS file? The problem I'm trying to solve is that I have a pin 
  defined in my schematic for attaching a wire to the PCB. There is
  no actual device to be installed. In order to get the pin to show
  up on PCB's rat's nest, I defined a dummy device with a hole for a 
  footprint. This allows the rat's nest to show that there's
  something that needs to be added to the PCB layout. The problem now
  is that the dummy device shows up in the BOM and is also being
  placed in the gerber XYRS file. So the question is how do I get the
  hole to be recognized by the rat's nest on PCB, but get omitted
  from the BOM and the XYRS exports?
 
 I usually put 'DNP' for 'Do Not Populate' in the 'Value' attribute
 and append a note in the file to that effect.  Most assembly houses
 know and work around that.  If not, then you get to write a handy
 script to scrub DNP lines or do it manually.
  I've also noticed that the BOM generated by the export function of
  PCB is showing the device's footprint rather than the device name
  for the description. Is this correct?
 I think that the intended/more common flow is to use gnetlist to 
 generate the BOM from the schematic.  There was a message on the list 
 just recently that pointed to the exact locations for generating BOMs.

Here's the command from my “update-partslist” script:

gnetlist -g bom Schematic.sch -o Parts_List.tsv

You need to create a file called “attribs” in the same directory as the
schematic (or in the current directory?  I'm not sure which, but in
this case the schematic *is* in the current directory).

value
footprint
description
manufacturer
manufacturer_partnum

These five lines in the attribs file define which attributes will be
used to select columns for the resulting tab-delimited output file.

Regards,
Colin


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Re: gEDA-user: Has anyone in this group seriously used KiCAD?

2011-08-22 Thread Colin D Bennett
On Mon, 22 Aug 2011 10:07:45 +0800
Atommann atomm...@gmail.com wrote:

 2011/8/20 Colin D Bennett co...@gibibit.com:
  On Fri, 19 Aug 2011 11:55:31 -0400
  John Hudak jjhu...@gmail.com wrote:
 
  Pros/cons?  and please, no philosphy about integrated vs
  independent tools...I am interested in aspects such as what things
  work? what doesn't? user experiences such as strengths and
  weakness (again actual/functional and not philosophy)
 
  I've not “seriously” used it, but I was just today frustrated when I
  tried to download and open the Maple Mini KiCad project ([1]) and my
  KiCad version (from Ubuntu 11.04 repositories) says the layout and
  schematic files are unrecognized types.
 
  More specifically, trying to open the .brd file says “Unknown file
  type” and trying to open the schematic says “file.sch is NOT an
  EESchema file!”  See screenshot at [2].
 
  A version incompatibility?  Maybe, but you would hope KiCad would at
  least tell the user that the file is the wrong version, rather than
  such cryptic errors.  User error?  Maybe, but how hard can it be to
  open a board file or schematic file?
 
 The Maple Mini was not designed with KiCAD, it was designed with
 Eagle.

Oh!
**MY APOLOGIES TO KICAD:** You did the best you could to try and open
the Eagle files.

LeafLabs: I think you owe *me* an apology! At least you could tell users
you what tool the .sch / .brd files were for!  I don't see anywhere in
the leaflabs GitHub repository or documentation that it says what EDA
tool the files belong to!

For instance, here's the compete section called Hardware Design Files
from the leaflabs-docs maple-mini.rst document:


Hardware Design Files

The hardware schematics and board layout files are available in the
Maple Mini GitHub repository.

From the GitHub repository main page, you can download the entire
repository by clicking the Download button. If you are familiar with
Git, you can also clone the repository at the command line with

$ git clone git://github.com/leaflabs/maplemini.git


I think the .sch extension is far too overloaded...

Regards,
Colin


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gEDA-user: pcb HID GUI options: gtk, lesstif?

2011-08-22 Thread Colin D Bennett
On Mon, 22 Aug 2011 16:51:03 -0400
DJ Delorie d...@delorie.com wrote:

 Which GUI ?

That makes me wonder:
who uses the Lesstif HID GUI instead of the GTK HID GUI?  I've only
used the GTK GUI because I don't know why one might choose Lesstif.

Any Motif/Lesstif applications I've used in the past are missing
the basic niceties of GTK such as the standard file open/save dialogs,
Unicode support, nicer text rendering (antialiased text), using my
chosen system widget/color/font styles, etc.  It's likely that new
versions have improved on these shortcomings, but I don't know.
Apparently the pcb Lesstif GUI is still actively used, so I pose the
question to pcb users:  if you use pcb with the Lesstif GUI, why?

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds - summary

2011-08-21 Thread Colin D Bennett
On Sat, 20 Aug 2011 08:09:37 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Fri, Aug 19, 2011 at 01:46:24PM -0700, Steven Michalske wrote:
  
  On Aug 19, 2011, at 1:39 PM, Vanessa Ezekowitz wrote:
  
   On Fri, Aug 19, 2011 at 12:41:58PM -0400, DJ Delorie wrote:
   [...]
   Though, I am still unsure how to indicate that the last 4
   layers can't be used for drawing.
   
   Put the item names in parenthesis.
   
  A little padlock icon is universal as a locked thingy.
 
 I will play with this idea. Probably I can fit a small padlock
 onto the bottom-right corner of the swatches. How clear this
 will be from a user perspective, I will not know until I try it.

I'm wondering if users will think the padlock icon should function as a
button to toggle the “locked” state of a layer, as in the GIMP.  In
this case, the layer is not so much locked as it is a “virtual” layer
that is computed based on other data.

Perhaps italicized text would be enough to at least indicate there is
something special about those layers.

Regards,
Colin


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Re: gEDA-user: Creating bill of materials?

2011-08-19 Thread Colin D Bennett
On Thu, 18 Aug 2011 16:05:30 -0400
John Hudak jjhu...@gmail.com wrote:

 So, this causes me to ask the question: Why hasen't gattrib been
 removed from:http://geda.seul.org/wiki/geda:gaf  as well as any
 other instances?
 
 While the concept is good, the implementation is worthless, and
 apparently has been 'around' with the same sort of problems since
 2006.

I agree gattrib is really poorly implemented.  However, I still find it
*extremely* useful to quickly enter (or even just examine) ‘value’ or
‘footprint’ attributes for many schematic components at once.

Importing a CSV into a spreadsheet program to edit it and re-export
back to CSV to import to gschem sounds like a big pain in the derrière.

Generally all I need is a really simple table to edit some values, and
it should only take a single step to access.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-19 Thread Colin D Bennett
On Thu, 18 Aug 2011 23:12:57 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Colin D Bennett wrote:
 
  I really dislike the double-click idea.  I often need to quickly
  enable/disable visibility of multiple layers, 
 
 Nothing beats accel-keys for fast actions. In this case [ctrl-N] or 
 [shift-N] would be the natural choice. 

I don't argue that in general, keyboard accelerators are a very fast
way of working.  But I can't see them being the best way of
quickly showing/hiding multiple layers.

I try to work with left hand in the qwerty home position and right hand
on the mouse (and no looking away from the screen).  Pressing Ctrl-7
means I have to look down at my keyboard and move my left hand from the
home position.  Also, without numbers on the layer buttons, the layers
after about #3 are not easily and without extra thought associated by a
human with the correct numeric index.  If I wanted to hide “vias”,
“pins/pads”, and “silk”, it would be tremendously harder to figure out
that I had to press Ctrl-6, Ctrl-8, Ctrl-9, rather than  just
click-click-click with the mouse directly on the layer's button.

  and the last thing I need is to have to double-click each button.
 
 A double click is a single action to me. 
 If you don't like double clicks, how about [control-click]?

Control-click is better for me.  Double-click requires my mouse to
pause for a moment longer than a single click, introducing
a discontinuity in the otherwise fluid move-click-move-click-move-click
process I would use to show/hide a set of layers.

  I would much prefer a small region on the button (or next to the
  button) that controls active/inactive. 
 
 Seems, our preference differs in this aspect. I'd rather not target 
 small areas for quick, fast actions. This is what we have now with 
 the toggle buttons. And I tend to mis-click every once in a while. 

I know about Fitts's law, but once my mouse is in the layers palette, I
don't have to move far to hide/show many layers at once, so I don't
mind if the Show/Hide button is relatively small.

Anyway, I think it makes sense to have both keyboard shortcuts and a
way to show/hide layers with the mouse.  Perhaps useful for different
purposes, but also based on personal preference.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-19 Thread Colin D Bennett
On Thu, 18 Aug 2011 22:22:11 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Thu, Aug 18, 2011 at 11:34:04PM +0200, Kai-Martin Knaak wrote:
  Andrew Poelstra wrote:
  
   I like KMK's
  click/double-click idea if possible.
   
   Very possible. But you would still be unable to toggle visibility
   independent of selection using the mouse. 
  
  Why is this so? Are double clicked items automatically selected 
  in GTK widgets?
 
 They are in a GtkTreeView. It's a nasty, inflexible widget.

In defense of GtkTreeView in this case :-)  I suggest that it would be
theoretically impossible for it to satisfy both
(a) good responsiveness to select an item when it is single-clicked, and
(b) allowing double-click on an item without selecting it.
  (Unless the program can predict a future event: whether the user
  will click again within the double-click time duration... if that
  is implemented, then we'll have more important concerns.)

Think about the sequence of events:


Case (a) the widget is optimized for good responsiveness to
clicks.

 Scenario (a.1): User selects an item.
 (1) Stimulus: User presses mouse button over widget.
 Response: Item under mouse is SELECTED.

 Scenario (a.2): User double-clicks an item.
 (1) Stimulus: User presses mouse button over widget.
 Response: Item under mouse is SELECTED.
 (2) Stimulus: User releases mouse button.
 Response: No response.
 (3) Stimulus: User presses mouse button.
 Response: Oh!  It's a double click.  Dispatch signal to widget.


Case (b) allow double-click on an item without selecting it.

 Scenario (b.1): User selects an item.
 (1) Stimulus: User presses mouse button over widget.
 Response: No response computer needs to wait to determine if a
 second click will follow.
 (2) Stimulus: User releases the mouse button.
 Response: No response computer STILL needs to wait to determine
 if a second click will follow.
 (3) Stimulus: Timeout has expired since (1) -- SELECT the item.
   User is thinking... Wow! the program is slow to react.

 Scenario B: User double-clicks an item.
 (1) Stimulus: User presses mouse button over widget.
 Response: No response computer needs to wait to determine if a
 second click will follow.
 (2) Stimulus: User releases mouse button.
 Response: No response computer waiting for possible double
 click.
 (3) Stimulus: User presses mouse button.
 Response: Oh!  It's a double click.  Dispatch signal to widget.




   How important is this to people? 
  
  Quite important. When working with four layer layouts I often 
  need to toggle visibility of layers while I keep working one
  of the inner layers.
  
   It bothers me, but only because there is no keyboard
   shortcut in Gtk for toggling visibility.
  
  I'd prefer to have both: Mouse click action and keyboard accels.
  
 
 I've gotten the swatch-clicking to work by catching mouse clicks
 over the visibility toggle column and preventing those clicks from
 propagating to the GtkTreeView.
 
 You say you don't want to reach for a tiny area with the mouse.
 I have increased the swatch size. Take a look at:
 
 http://wpsoftware.net/andrew/dump/mockup3.png

Simple, functional, beautiful.  A+

 The swatches are far larger than the radio buttons, have more
 visibly clickable area (as they are square), and contrast with
 their surroundings more.

I like it.

Regards,
Colin


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Re: gEDA-user: Commandline option --menu-file

2011-08-19 Thread Colin D Bennett
On Fri, 19 Aug 2011 16:44:12 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

d) While menues can be ripped off and used as a toolbox, they
 don't remember their state beyond the end of the session. This
 essentially prevents persistent user configuration of the GUI. 

Actually, the GTK tear-off menus are currently broken.  I can tear off
menus, but the items cannot be activated by clicking them.

I used to use the View | Grid Size menu as a tear-off menu constantly,
and it was very helpful.  I really miss it, but was hoping the “New
Grids” feature would be finished and pushed to mainline pcb to
supercede that need.

Regards,
Colin


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Re: gEDA-user: Has anyone in this group seriously used KiCAD?

2011-08-19 Thread Colin D Bennett
On Fri, 19 Aug 2011 11:55:31 -0400
John Hudak jjhu...@gmail.com wrote:

 Pros/cons?  and please, no philosphy about integrated vs independent
 tools...I am interested in aspects such as what things work? what
 doesn't? user experiences such as strengths and weakness (again
 actual/functional and not philosophy)

I've not “seriously” used it, but I was just today frustrated when I
tried to download and open the Maple Mini KiCad project ([1]) and my
KiCad version (from Ubuntu 11.04 repositories) says the layout and
schematic files are unrecognized types.

More specifically, trying to open the .brd file says “Unknown file
type” and trying to open the schematic says “file.sch is NOT an
EESchema file!”  See screenshot at [2].

A version incompatibility?  Maybe, but you would hope KiCad would at
least tell the user that the file is the wrong version, rather than such
cryptic errors.  User error?  Maybe, but how hard can it be to open a
board file or schematic file?

Oh another note, I like how gEDA puts its symbols and footprints in
separate files -- it is great for version control and for
browsing/searching with standard file management tools or directly on a
GitHub repository view, etc.

Regards,
Colin

References
--

[1] Maple Mini schematics and layout
https://github.com/leaflabs/maplemini.

[2] Screen shots of attempting to open Maple Mini schematic with KiCad.
http://gibibit.com/upload/2011-08-19_KiCad_MapleMini_error.png



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Re: gEDA-user: PCB+GL rebased to git HEAD (with nanometers)

2011-08-19 Thread Colin D Bennett
On Fri, 19 Aug 2011 15:08:57 -0400
Dave McGuire mcgu...@neurotica.com wrote:

 On 08/19/2011 12:18 PM, Peter Clifton wrote:
  My PCB+GL branches are now rebased against git HEAD, with all the
  excellent work from Andrew Poelstra on the internal unit conversion
  to nanometers.
 
  Please test and let me know if you find any bugs. I've given it
  cursory testing, but haven't actually used it much myself yet.
 
Hey Peter!  Thank you for all of your excellent work.
 
If I may make a suggestion...For those of us who don't access the 
 repository regularly, and don't live and breathe git (I'm an SVN
 guy), it might be helpful to put a quickie command line (or two) in
 these sorts of announcements to tell us how to actually get that code.

Peter Clifton's PCB+GL repository instructions:
http://pcjc2.blogspot.com/2011/02/pcbgl-repository-instructions.html.


Personally, I use Bazaar with the bzr-git plugin to access all the gEDA
git repositories.  That way I don't have to learn git's command
scheme... :)

For me, using bzr-git, the commands look like:

1. bzr git-import git://repo.or.cz/geda-pcb/pcjc2.git
2. bzr checkout --lightweight pcjc2.git/refs/heads/pcb+gl work-gl
3. cd work-gl  ./autogen.sh  ./configure  make

I think it's simpler than the native git commands, but maybe that's
just me.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-18 Thread Colin D Bennett
On Thu, 18 Aug 2011 07:48:31 +0200
Bert Timmerman bert.timmer...@xs4all.nl wrote:

  I think such a thing would look like:
  http://wpsoftware.net/andrew/dump/selector.png
  
  What do people think of this? 

 IMHO, the former proposal with visibilty buttons without rectangles
 is the improvement we are looking for, and we should exploit screen
 real estate more aggressively and maybe even go as far as truncate
 layernames to 6..8 chars.

If you shorten the layer names here, where would you even want the full
names?  I think if the user has given layers long names, it is for a
good reason.  This is about the only place the layer names are even
used, except for the exported Gerbers.  If the user wants short layer
names, he can just name his layers with short names.

I do think it could be useful to allow the font size for the layer
names to be configurable in the preferences, and allow the user to
adjust the width of the left side panel.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-18 Thread Colin D Bennett
On Thu, 18 Aug 2011 09:25:06 -0700
Jared Casper jaredcas...@gmail.com wrote:

 On Thu, Aug 18, 2011 at 3:56 PM, Andrew Poelstra as...@sfu.ca wrote:
 
   2. Whenever you hide a layer, the selector would jump to the
  previously-selected layer. I haven't tried it yet, but I
  think that from a user's perspective that would make the
  visibility buttons seem independent of list selection.
 
 
 This would work for hiding layers, but not making them visible.  If
 layer X is active and layer Y is invisible, how do I make layer Y
 visible without making it the active layer?  I like KMK's
 click/double-click idea if possible.

I really dislike the double-click idea.  I often need to quickly
enable/disable visibility of multiple layers, and the last thing I need
is to have to double-click each button.  I would much prefer a small
region on the button (or next to the button) that controls
active/inactive.  I like the color swatch and how it shows a small
rectangle of the layer color when the layer is hidden; if this swatch
were the show/hide toggle, that would be very slick.

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-18 Thread Colin D Bennett
On Thu, 18 Aug 2011 18:57:33 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Thu, Aug 18, 2011 at 09:50:25AM -0700, Colin D Bennett wrote:
   I like the color swatch and how it shows a small
  rectangle of the layer color when the layer is hidden; if this
  swatch were the show/hide toggle, that would be very slick.
 
 That is how I would like it to work. But clicking the swatch
 also selects the layer, which is undesirable behavior. There
 is no clean way to prevent this with a GtkTreeView widget.

It doesn't sound like a “tree view” is the most appropriate concept for
the layer list.  There is no apparent visual hierarchy.  I am not
familiar with GTK, but is there another widget that would be more
suitable?  E.g., table, list, general scrollable canvas with custom
widgets stacked vertically?

Regards,
Colin


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Re: gEDA-user: Nanometer conversion pushed to git head

2011-08-17 Thread Colin D Bennett
On Tue, 16 Aug 2011 23:11:13 -0400
DJ Delorie d...@delorie.com wrote:

 
  EVERY time I draw a new footprint, I spend half the time figuring
  out where the “imaginary” line endpoint should lie.
 
 I just use the rectangle tool.

Oh!  I forgot you can use the rectangle tool to make pads too.  That
could be very helpful.

I do 99% of my footprints in a text editor, however, since I can keep
the content clean and organized that way, with lots of comments, and I
can do easy, direct entry of coordinates (easy mainly except that I
have to convert to the imaginary-line-endpoint style of coordinates for
pads).

Regards,
Colin


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Re: gEDA-user: Layer button backgrounds

2011-08-17 Thread Colin D Bennett
On Wed, 17 Aug 2011 20:48:48 +0200
Felix Ruoff fe...@posaunenmission.de wrote:

 I personally like the new style you created. Its very nice! I think
 the reason for adding this small rectangles is, that its easier to
 see, if the button is pressed.

Good point.  I do like the full color fill you show, Andrew.  However,
I think we need a better way of indicating which layers are visible.
Perhaps a little X or checkbox icon on the button?  I already dislike
the current buttons' indication of which layers are visible (change of
fill color and text color with inset or outset border). Maybe something
better can be done.

Regards,
Colin



 Am 18.08.2011 04:00, schrieb Andrew Poelstra:
  Hey all,
 
  I am working on moving the Gtk layer-selector into its
  own widget (see bug 699482, for example), and cleaning
  up the code.
 
  A question I have for the group is: why are the backgrounds
  of the layer buttons in little rectangles? Is there
  opposition to making the background fill the whole buttons,
  like so?:
 
  http://wpsoftware.net/andrew/dump/buttons.png
 
  It would simplify the code a bit and IMHO looks more modern.
  There is a bit of an optical illusion making the new buttons
  seem bigger, but I checked in gimp and there is no change in
  size.


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Re: gEDA-user: Layer button backgrounds

2011-08-17 Thread Colin D Bennett
On Wed, 17 Aug 2011 23:01:30 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Thu, Aug 18, 2011 at 07:31:24AM +1000, Stephen Ecob wrote:
   Good point.  I do like the full color fill you show, Andrew.
    However, I think we need a better way of indicating which layers
   are visible. Perhaps a little X or checkbox icon on the button?
    I already dislike the current buttons' indication of which
   layers are visible (change of fill color and text color with
   inset or outset border). Maybe something better can be done.
  
  Photoshop (and also GIMP) use a small on/off icon that looks like an
  eye to control layer visibility. This may or may not be a good way
  to do it, but it is certainly a familiar UI to many people.
 
 
 I think such a thing would look like:
 http://wpsoftware.net/andrew/dump/selector.png
 
 What do people think of this? 

That looks very nice -- status is easily apparent.  I think we could
compact the layout by eliminating excess horizontal and vertical
spacing.

Why is “Signal” bold in that image?  The bad thing about using
Bold/Normal weight for indicating status is that it changes the width
dynamically and might or might not cut off the text.

Regards,
Colin


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Re: gEDA-user: Gschem and footprints

2011-08-16 Thread Colin D Bennett
On Tue, 16 Aug 2011 15:35:46 -0500 (CDT)
kqt4a...@comcast.net wrote:

 I am sure this has been done to death but I have to ask
 I am a beginner and the way I am using gschem and pcb is quite awkward
 I open my schematic in gschem and open pcb
 Then when I add a component in gschem I switch to pcb to search for a
 footprint When I find the proper footprint in pcb I switch back to
 gschem and manually edit the properties to add the footprint name
 I MUST be doing something wrong

You're not doing anything “wrong”.  There are many “right” ways of
working with gEDA... it allows you the freedom to choose what works
best for you. If switching back and forth between pcb and gschem is
tedious, then consider the following suggestions as just a few of the
possible optimizations you can make to your process.

I almost never use pcb's footprint browser.  Yes, the default pcb
footprint library has a lot of symbols with obtuse names, so it is
difficult to find the one you need by name.  However, I only use a few
of the default footprint library's footprints--for instance: JUMPER4,
RESC1608N, CAPC1608N, ... and most of my footprints are custom ones I
have created myself.

The footprints in my own library have extremely descriptive names and
all I need is a file manager window listing the available footprint
files and I can pick the correct footprint by name.  For instance, here
are some footprint file names from my library:

Abracon_ABM8G.fp
ADAM_TECH_2PH_2.00_mm_pin_header_SMT_2_pin.fp
ADAM_TECH_2PH_2.00_mm_pin_header_SMT_3_pin.fp
ADAM_TECH_2PH_2.00_mm_pin_header_SMT_4_pin.fp
Antenna_Inverted_F__Ember__2.4GHz__62milFR4.fp
Antenna_Meandered_Inverted_F__2.4GHz__TI_AN043.fp
APEM_MJTP1230_6mm_tactile_switch__4pin.fp
APEM_MJTP1230_6mm_tactile_switch__P1_P4.fp
Bourns_3309W-1_Trim_Pot.fp
Castellated_Via__D20mil_W36mil_L40mil.fp
Castellated_Via__D45mil_W60mil_L50mil.fp
CK_KMT0.fp
DFN8_2x3_Microchip_MC.fp
DPAK_Pin2IsTab.fp
DPAK_Pin4IsTab.fp
FCI_10033526-N3212MLF.fp
FCI_98424-x52-06.fp
Header_1x3_100mil.fp
Header_2x10_100mil_rcnum.fp
Header_2x3_100mil_rcnum__with_IDC_receptacle_outline.fp
Hirose_DF13A-2P-1.25H.fp
Kemet_EIA_6032-28_DensityB.fp
Kingbright_SA56-11EWA.fp
Kingbright_SA56-11EWA__Oval_pads__Max.fp
LED1608M_logical_pins.fp
Molex_KK-156_male_header_3pin.fp
Molex_KK-156_male_header_8pin.fp
MSOP8_Microchip_MS.fp
Murata_CSTCE.fp
Murata_LDB18.fp
Nichicon_Aluminum_Electrolytic_Capacitor_UX_10x10.fp
NKK_UB_Pushbutton_SK_SPDT.fp
NXP_LQFP-48_7x7_SOT313-2.fp
Omron_XF2M-2015-1A_RefPin1.fp
Omron_XF2M-2015-1A_RefPin20.fp
Optek_OVS5MxBCR4_LED.fp
OSRAM_LA_LS_LY_E65F_LED__IR_reflow.fp
OSRAM_LR_LY_T68F_LED__basic_reflow.fp
OSRAM_M676_LED.fp
Phoenix_Contact_1984620__Pin1OnRight.fp
QFN32_5_EP_multi_opening.fp
R_0603_Walsin.fp
SOIC-8N_Exar_IntelGuidelines.fp
SOT-23_Microchip_TT.fp
SOT23__MOSFET_1G_2S_3D.fp
SOT353_NXP.fp
SOT-89_Microchip_MB.fp
SSOP-20_Microchip_SS.fp
SSOP-28_FTDI_IntelGuidelines.fp
ST_LQFP48.fp
Tag-Connect_TC2030-MCP.fp
Tag-Connect_TC2030-MCP-NL.fp
Tag-Connect_TC2030-MCP-NL_PlatedHoles.fp
Tag-Connect_TC2030-MCP_PlatedHoles.fp
Test_Pad_0.8mm.fp
Test_Pad_1.0mm.fp
Test_Pad_1.27mm.fp
TSOP-5.fp
Tyco_1734035.fp
Vishay_Dale_XT49M_SMD_crystal.fp

You should be able to understand the purpose of each footprint by its 
nae and perhaps a quick Google on the package code or part number.

I also occasionally have used footprints from gedasymbols.org.  The
gedasymbols.org web site has a great interface for searching the
footprint library and previewing the footprints.

Another thing you can do to save time is to defer footprint attribute
assignment until you have the schematic mostly drawn.  Then you can do
footprint assignment quickly.  You can use either gschem or the
“gattrib” tool to quickly assign footprints to all symbol instances
in a schematic.

I highly suggest you become proficient at creating your own footprints
since you will often run into new parts without a pcb footprint, and
this allows you to keep a consistent footprint style matching your own
preference (you might have your own preference about silk screen
outline style, etc.).  Creating footprints was tedious for me at first,
but now after making several dozen, it has become really simple.  I just
grab a calculator (or the qalculator application), a pencil and paper,
and lay out the footprint per the manufacturer's package drawing and
recommended land pattern.  I usually create the footprint file (*.fp)
with a text editor since it's easy to get the exact layout that way,
but on occasion I will use pcb to draw the footprints graphically, or
make minor edits to hand-made footprint files.

This is surely not exactly the type of answer you were expecting, but
gEDA is such a flexible tool that there is no single right answer...

Regards,
Colin


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Re: gEDA-user: Nanometer conversion pushed to git head

2011-08-16 Thread Colin D Bennett
On Tue, 16 Aug 2011 23:53:21 +0100
Peter Clifton pc...@cam.ac.uk wrote:

 I have some ideas about how pad-stacks could be made more general
 though, so a square pad (like many others) is just a special case of a
 polygon - which can, of course.. be rotated arbitrarily, either at the
 pad level, or on the component level.

+1

EVERY time I draw a new footprint, I spend half the time figuring out
where the “imaginary” line endpoint should lie.  In reality footprints
are defined by the actual edge of the pad, not by the endpoints of an
imaginary line W/2 units from the end of the pad (“end” depending on
the dimension having greatest length...).

I'd really like to be able to SWIM: Say What I Mean.  Nobody actually
cares where these imaginary pad line endpoints are, but we are required
to specify them nonetheless.

Regards,
Colin


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Re: gEDA-user: Line Thickness in Imported DXF Files; Rotating by Arbitrary Angle; UTF-8

2011-08-15 Thread Colin D Bennett
On Sun, 14 Aug 2011 01:48:42 -0400
Gus Fantanas fanta...@innocent.com wrote:

 Third, can pcb handle UTF-8 characters? On the silkscreen I want the
 Ω character to appear (for Ohms, as in 50Ω). The text entry window 
 accepts the Ω just fine, but then the text on the silkscreen displays 
 /two/ blocks for it. gschem seems to display Ω in text and μ in
 values fine, but it may have trouble printing these characters.

My workaround for better text support is to draw the text in Inkscape
using whatever TrueType/OpenType fonts I want (full Unicode, of course)
and even adding graphics in some cases (board logos, etc.).  Then
export to EPS, use pstoedit to convert to pcb format.  (There are some
problems with bad polygon shapes in pstoedit's output, however.  I think
DJ has a script that will fix the output from pstoedit so it works
better in pcb.)

Using Inkscape to make the text allows much more beautiful text than
the default pcb font.  I have tested it on real boards' silk screen and
found that using Inkscape with fonts like Droid Sans provides much
greater readability and superior appearance to the default pcb font at
similar character sizes.  Not to mention you can use the full Unicode
character set and include graphics as well.

The main downsides are 
(1) if you want to change the text, you have to edit your .svg in
Inkscape and re-import into pcb, then re-position the polygons
composing the text; and
(2) if you have a lot of text and/or graphics on the board imported
from Inkscape, then it can be tricky to select, move, or delete
individual strings because the little polygons composing the text or
graphics are not grouped in any way, so you need to carefully make sure
you select all the polygons for the text you want to move without
selecting any bits of other text.

Regards,
Colin


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Re: gEDA-user: personal component library frustration-HELP/suggestions please?

2011-08-15 Thread Colin D Bennett
On Mon, 15 Aug 2011 14:23:15 -0400
John Hudak jjhu...@gmail.com wrote:

 I've created two directories in my home directory to store symbol
 files that I create, and another directory to store footprints I
 create: /home/jjh/project/component_symbols
 /home/jjh/project/component_footprints
 
 How do I modify gschem to look in my home directory for symbols AS
 WELL AS THE DEFAULT symbol directory? e.g I want my symbol directory
 in my user directory to appear in the Select Component component
 selection window.
 
 If you have a suggestion on how to organise this in a better way,
 please let me know, and also tell me how to implement it.
 gschem v 1.6.1.20100214

I can't tell you if it's a “better” way for you, but I will tell you
what I do, and why I do it:

I do not let gschem know about the location of my own symbol library.
Instead, I always store copies of the custom symbols I use in a
project (and that is virtually all symbols, now) in the project
itself.  This way, I can take any snapshot of that project, some time
in the future, and open it in gschem without any surprises such as
“major symbol changes detected!”.  Because gschem normally only stores
references to symbols in the schematic, your schematics are FRAGILE to
symbol file changes.

For instance, I recently wanted to shorten the pin on my “signal
ground” symbol in my personal library.  Instead of 200 units, I made
the pin 100 units in length. (Now it's consistent with the Vcc power
rail symbol I use, so it looks much better in common situations like
decoupling caps, etc.)

If I had schematics that included references to this Signal_ground.sym
file that I modified, those schematics would be BROKEN!  Because the
existing net lines would no longer terminate on the end of the
Signal_ground.sym pin.

When I do want to make use of new symbols in an existing project, it's
a simple matter of copying the new symbols from my symbol-library
project into the circuit design project's “Symbols” subdirectory.
(I maintain my symbol/footprint library independently from any specific
schematic design projects, and it is separately version-controlled).

Of course, the downside is that you don't immediately have a list of
all your symbols in gschem's component library window when you start a
new project.  No big deal, just copy the symbols from the component
library into your new design project's Symbols directory as you need
them.  This small effort is, for me, completely worth it for the
robustness provided by avoiding dependency on external symbol
libraries.  It allows me to feel bold about making improvements to my
symbol library without requiring extreme measures to ensure
compatibility with existing schematics.

Regards,
Colin


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Re: gEDA-user: Bug in 'FreeRotateBuffer()'? (WAS: Re: Line Thickness in Imported DXF Files; Rotating by Arbitrary Angle; UTF-8)

2011-08-15 Thread Colin D Bennett
On Mon, 15 Aug 2011 19:24:34 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Mon, Aug 15, 2011 at 11:29:59AM -0700, Colin D Bennett wrote:
  Because of this bug (it is completely a bug from the user's point of
  view), as you suggested I always make my nominally-square pads
  slightly non-square.  Usually by +/- 0.01 mil or +/- 0.02 mil, but
  that might not be enough for good rotation... hopefully nanometer
  conversion will improve that significantly with no extra effort for
  us footprint designers.
 
 The problem is that the file-format still saves in cmils. (You can
 use a text-editor to put the new units in, but then you have problems
 with backward-compatibility.)

Perhaps after the nanometer conversion has been thoroughly run through
its paces in mainline pcb for a while, and we feel it is rock-solid, we
can add a Preferences option to save .pcb files with coordinates and
lengths in nm rather than cmil.

Regards,
Colin


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Re: gEDA-user: personal component library frustration-HELP/suggestions please?

2011-08-15 Thread Colin D Bennett
On Mon, 15 Aug 2011 22:02:07 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 /-- YOUR-PROJECT.g2p ---
 schematics YOUR-PROJECT.sch
 output-name YOUR-PROJECT
 elements-dir
 FULL-PATH-TO-THE-DIR-BELOW-THE_DIRS-THAT-CONTAIN-YOUR-FOOTPRINTS
 \--- I always add the
 options skip-m4 and use-files because I don't want any of the M4
 generated footprints, ever. But this may be due to personal prejudice.

I can't see any reason NOT to use the skip-m4 option.  Every footprint
in the default pcb library is available as a newlib-format footprint,
right?

Advantages of using skip-m4:

+ Avoids that nasty bug that occurs when a footprint name contains a
  hyphen character (-).

Disadvantages of using skip-m4:

- Can't use your own custom m4 footprints directly?


Regards,
Colin


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Re: gEDA-user: personal component library frustration-HELP/suggestions please?

2011-08-15 Thread Colin D Bennett
On Mon, 15 Aug 2011 22:24:24 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Colin D Bennett wrote:
 
   No big deal, just copy the symbols from the component
  library into your new design project's Symbols directory as you need
  them.  This small effort is, for me, completely worth it for the
  robustness provided by avoiding dependency on external symbol
  libraries.  It allows me to feel bold about making improvements to
  my symbol library without requiring extreme measures to ensure
  compatibility with existing schematics.
 
 gschem almost allows a much more convenient way:
 
 1) Draw the schematics with symbols from a central lib.
 
 2) embed all the symbols in the schematics. This puts a copy of the
 symbol in the *.sch file rather than just a reference.

Thanks for pointing this out.

However, I guess you can easily forget to embed one or two symbols.
I prefer a strict and robust process, even if it requires manual
intervention (e.g., to copy a file) once in a while.

 That way, changes in the lib do not affect the schematic at all. 
 Unfortunately, does exactly the opposite. That is, it removes the 
 local copy of the symbol in favor of a rererence to a sym-file in 
 the library. The nasty side effect is that you may get an incompatible
 version of the symbol.

How do you update the symbols in a schematic when you actually wish to
do so when they are embedded?  Hopefully you don't have to delete and
re-add them... that would require re-adding all customized attribute
values too.

 In addition, there is no way to export the 
 embedded symbol to some local directory. (Of course you can use a
 text editor and copy/paste)

Could you do Hs hierarchy down-symbol and then save it from there?

Regards,
Colin


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Re: gEDA-user: Layer selective DRC

2011-08-13 Thread Colin D Bennett
On Sat, 13 Aug 2011 19:34:38 +0200
Levente Kovacs leventel...@gmail.com wrote:

 On Fri, 5 Aug 2011 17:36:25 + (UTC)
 Sparky scop...@gmail.com wrote:
 
  For my outline layer I did the following to add the attribute:
Edit-Edit attribute of-CurrentLayer
Left box:  PCB::skip-drc
Right box: 1
 
 I'm sorry for the late answer.
 
 I'm not sure if you need this for the layer called outline.
 
 For the others, thank you for taking time playing with it. I didn't
 experienced any trouble with the feature. However, I'm not a heavy
 DRC user.

I get line too narrow errors for my outline layer, due to the 1 mil
lines with which I draw the outline.

Also, and not completely related in the current DRC implementation, my
outline layer makes pcb think there are unintended connections when it
intersects vias near the edge (e.g., castellated vias) creating what
appears to pcb to be a circuit from a net on another layer, to the
outline, to another net on a non-outline layer.

Regards,
Colin


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Re: gEDA-user: Tag-Connect TC2030-MCP(NL) footprint, expert review

2011-08-12 Thread Colin D Bennett
On Fri, 12 Aug 2011 11:04:54 -0700
Colin D Bennett co...@gibibit.com wrote:

 I've created gEDA/pcb footprints for the Tag-Connect
 TC2030-MCP / TC2030-MCP-NL connectors.  The TC2030 family of cables
 have a special connector using spring-pin (aka pogo-pin) contacts and
 do not require any BOM part: the only requirement is proper SMT pad
 layout with correct alignment holes.

P.S. I forgot to link to Tag-Connect http://www.tag-connect.com/
and the data sheets with layout diagrams at

TC2030-MCP Data sheet
  http://www.tag-connect.com/Materials/TC2030-MCP%20Datasheet.pdf

TC2030-MCP-NL Data sheet
  http://www.tag-connect.com/Materials/TC2030-MCP-NL%20PCB%20Footprint.pdf

Regards,
Colin


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Re: gEDA-user: PCB nanometer git tree

2011-08-12 Thread Colin D Bennett
On Fri, 12 Aug 2011 23:31:39 +0200 (CEST)
k...@aspodata.se (Karl Hammar) wrote:

 Andrew Poelstra:
  On Thu, Aug 11, 2011 at 09:30:34PM +0200, Karl Hammar wrote:
 ...
   -#define LARGE_VALUE(LONG_MAX / 2 - 1) /* maximum
   extent of board and elements */ +#define LARGE_VALUE
   LONG_MAX /* (LONG_MAX / 2 - 1) maximum extent of board and
   elements */
 ...
   Why do you want to use only half the range?
 
  So that the width of a max width box can be calculated as
  LARGE_VALUE - (-LARGE_VALUE) without overflow,
 
 Hmm, wouldn't it be better to use unsigned here?

IMHO, the many subtle pitfalls that crop up when unsigned arithmetic
is used throughout a large C program far outweigh the benefit of the
extra half-scale range.  Compiler warnings from gcc can catch some
problems (certainly not all) and usually it takes tons of effort to
make the code “warning-clean” when you enable all the signed-unsigned
type warnings.  In my experience, I've found that, it is best to avoid
unsigned arithmetic as much as possible.

Regards,
Colin


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Re: gEDA-user: Version compatibility between gschem and PCB

2011-08-11 Thread Colin D Bennett
On Thu, 11 Aug 2011 10:03:31 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Thu, Aug 11, 2011 at 10:40:51AM -0400, John Hudak wrote:
 I came across an board layout file that requires a newer version
  of PCB than I have installed.  My version of PCB is 20091103.  If I
  upgrade to the most recent version of PCB, will it be able to
  interoperate with gschem 1.6.1.20100214?
 
 The programs aren't really linked. What do you mean by interoperate?
 
 In any case, the only file format change from 2007 to 2010 was to add
 holes in polygons. I can't imagine gschem would know or care about
 this.

I guess the only things linking gschem and pcb are the netlist output
by gnetlist from the .sch file, and if you use gsch2pcb then it
generates the .pcb file with the right footprints instantiated as
elements.  Although new pcb versions have the Import Schematics feature
which somehow reads the gschem .sch files (does it call out to
gnetlist or other tools, or is it self-contained?).

 Also, a clarification of terminology for me is needed.  The PCB
  website ([1]http://pcb.gpleda.org/) lists a number of
  'snapshots'..are these beta releases or are they the most
  recent releases for distribution?
 
 The snapshots are official releases -- at least, they are what appear
 in distributions. I believe they are called as such because we ran out
 of version numbers at 1.99z and haven't decided what to do about it.

It's easy.  Increment the version number to 1.100.

Regards,
Colin


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Re: gEDA-user: Automatically start wire placement when you press the hotkey?

2011-08-11 Thread Colin D Bennett
On Thu, 11 Aug 2011 08:34:58 -0700
yamazakir2 yamazak...@gmail.com wrote:

 I agree, magnetic mode is an instant disable for me everytime I
 install gschem

Agreed... I like the idea of magnetic mode, especially when drawing
nets when zoomed out pretty far--it can be hard to click exactly on the
tip of the pin to which you want to connect.  However, it usually
decides to draw the net directly through other components and sometimes
even intersects the tips of other pins, causing erroneous connections!!!

What might be ideal would be the opposite of the current mode:
an opt-in rather than opt-out use of the modifier key.  Suppose
magnetic net mode could be activated momentarily by
Ctrl+clicking.  You could easily and without extra effort click
intermediate points to route the net line where you want it to go, then
finally tell gschem to terminate the net line on a pin by Ctrl+clicking
“approximately” on the tip of the pin to end it there.

Another thing that might make working with nets easier is it took fewer
clicks to move vertices.  Similar to how it is often irritating to have
to (1) Click, (2) Pause, (3) Click+Drag a symbol to move it *, 
to move a line you have to click it, then click and drag either the
line itself or one of its endpoints.  Whenever I move a symbol after
drawing nets to it, it's a little irritating to have to click so many
times to alter the lines.  Especially if I move a symbol perpendicular
to the net lines attached to it, then the net lines become
non-orthogonal (not parallel to X or Y axis) so I have to move TWO
vertices in general if I have an “L” in the net, because moving the
vertex on one lines doesn't also move the other line sharing that
vertex...

* I know about the 'm' key now and I do use it often, but it's still
  annoying to not be able to just click and drag a component in one
  smooth action, as new users expect to be able to do.

Regards,
Colin


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Re: gEDA-user: Version compatibility between gschem and PCB

2011-08-11 Thread Colin D Bennett
On Thu, 11 Aug 2011 10:40:51 -0400
John Hudak jjhu...@gmail.com wrote:

 I came across an board layout file that requires a newer version of
 PCB than I have installed.  My version of PCB is 20091103.  If I
 upgrade to the most recent version of PCB, will it be able to
 interoperate with gschem 1.6.1.20100214?

I am sure that it will.  I have been running pcb git HEAD
(bleeding-edge) for a year or so, and still using the gEDA/gschem from
Ubuntu repositories.  Currently I use gschem 1.6.2 (on Ubuntu 11.04)
with pcb git HEAD and it works fine.

The gEDA file formats are stable and compatibility has been
well-maintained.

 Another related question.  I am running gschem and PCB under Ubuntu
 10.10, Maverick Meerkat.  Are there any issues in upgrading PCB for
 this version of Ubuntu?

I doubt it.  Until a couple of months ago, I was running Ubuntu 10.04
with the latest pcb git HEAD -- no problem.

 I guess a related question is where can I find the most recent package
 release of gEDA for this version of Ubuntu.

I wonder if anyone has a Launchpad PPA for gEDA?

Regards,
Colin


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Re: gEDA-user: Automatically start wire placement when you press the hotkey?

2011-08-11 Thread Colin D Bennett
On Thu, 11 Aug 2011 21:50:31 +0200
Krzysztof Kościuszkiewicz k.kosciuszkiew...@gmail.com wrote:

 2011/8/11 Colin D Bennett co...@gibibit.com:
 
  Another thing that might make working with nets easier is it took
  fewer clicks to move vertices.  Similar to how it is often
  irritating to have to (1) Click, (2) Pause, (3) Click+Drag a symbol
  to move it *, to move a line you have to click it, then click and
  drag either the line itself or one of its endpoints.  ...
 
  * I know about the 'm' key now and I do use it often, but it's still
   annoying to not be able to just click and drag a component in one
   smooth action, as new users expect to be able to do.
 
 The click and drag is also partiallty fixed:
 http://git.gpleda.org/?p=gaf.git;a=commit;h=7f88749446b61493e881ad6aeb0a82f909a8c0d7
 
 commit 7f88749446b61493e881ad6aeb0a82f909a8c0d7
 Author: Peter Clifton pc...@cam.ac.uk
 Date:   Mon Mar 21 22:51:23 2011 +
 
 gschem: Don't require select to drag objects

Oh yeah!  I remember hearing about that.  Thanks for the reminder.  I
just haven't ever bothered yet to compile my own gschem from source so I
don't get all the new goodies...

Regards,
Colin


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Re: gEDA-user: PCB nanometer git tree

2011-08-10 Thread Colin D Bennett
On Wed, 10 Aug 2011 16:04:47 -0700
Andrew Poelstra as...@sfu.ca wrote:

 Please test this and let me know what needs to be done. Thanks!

OK, I have noticed one bug.  If I draw some lines on a copper layer,
two strange things occur:

(1) When I click on a line, it becomes highlighted and is selected.  If
I then click another line, it is also highlighted, but the first line
remains highlighted as well.  Every line clicked adds to the set of
highlighted lines.  I can, however, deselect a line by Shift-clicking
it.

(2) If I click and drag a *non-selected* line, I can move it OK.
However, if I try to drag one or more selected lines, they vanish.

Regards,
Colin


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Re: gEDA-user: PCB nanometer git tree

2011-08-10 Thread Colin D Bennett
On Wed, 10 Aug 2011 16:04:47 -0700
Andrew Poelstra as...@sfu.ca wrote:

 Please test this and let me know what needs to be done. Thanks!

Nice work!  So far it all looks great.  I haven't stressed it with
any fancy layouts yet, but all I can say so far is WOW and thanks for
your effort.

I'll let you know if I find any issues.  (I am having some difficulty
with my pointer snapping to the wrong pad -- not the one actually
nearest the cursor -- but I think this is in pcb git HEAD too.)

Regards,
Colin


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Re: gEDA-user: PCB nanometer git tree

2011-08-10 Thread Colin D Bennett
On Wed, 10 Aug 2011 22:16:38 +0200 (CEST)
k...@aspodata.se (Karl Hammar) wrote:

 Andrew Poelstra:
  I have a pcb branch available here for testing:
  
git clone git://wpsoftware.net/pcb-andrew.git
git checkout coord6
  ...
 Making all in doc
 make[2]: Entering directory
 `/var/home/karl/Net/Hmm/git/pcb-andrew/doc' gawk -f ./ascii2texi.awk
 ncol=3 fractional_size.tab  fractional_size.texi gawk
 -f ./ascii2texi.awk ncol=3 letter_size.tab  letter_size.texi gawk
 -f ./ascii2texi.awk ncol=3 metric_size.tab  metric_size.texi gawk
 -f ./ascii2texi.awk ncol=3 wire_size.tab  wire_size.texi ../src/pcb
 -x png --only-visible --font-path ../src --outfile pad.png pad.pcb
 sh: 
 /var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/ListLibraryContents.sh:
 No such file or directory Can't change working directory to
 '/var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/newlib'
 chdir() returned: 'No such file or directory' Can't change working
 directory to
 '/var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/pcblib-newlib'
 chdir() returned: 'No such file or directory'
 
  ...
 
 gd warning: one parameter to a memory allocation multiplication is
 negative or zero, failing operation gracefully png_do_export():
 gdImageCreate(-8195, -8305) returned NULL.  Aborting
 export. ../src/pcb -x eps --only-visible --font-path ../src
 --eps-file pad.eps pad.pcb
 sh: 
 /var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/ListLibraryContents.sh:
 No such file or directory Can't change working directory to
 '/var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/newlib'
 chdir() returned: 'No such file or directory' Can't change working
 directory to
 '/var/home/karl/Net/Hmm/git/pcb-andrew/src/../share/pcb/pcblib-newlib'
 chdir() returned: 'No such file or directory' make[2]: *** [pad.eps]
 Segmentation fault make[2]: *** Deleting file `pad.eps' make[2]:
 Leaving directory `/var/home/karl/Net/Hmm/git/pcb-andrew/doc'
 make[1]: *** [all-recursive] Error 1 make[1]: Leaving directory
 `/var/home/karl/Net/Hmm/git/pcb-andrew' make: *** [all] Error 2

I get similar errors regarding the missing directory, but no
segfault, and the make process did not bail out for me, so I didn't
notice the errors at all the first time I tried it. It proceeded past
the pad.eps stuff and finished the make process:

-- ... 
make[3]: Leaving directory `/home/cdb/Code/pcb/work/asp-coord6.2/doc'
make[2]: Leaving directory `/home/cdb/Code/pcb/work/asp-coord6.2/doc'
make[2]: Entering directory `/home/cdb/Code/pcb/work/asp-coord6.2'
make[2]: Nothing to be done for `all-am'.
make[2]: Leaving directory `/home/cdb/Code/pcb/work/asp-coord6.2'
make[1]: Leaving directory `/home/cdb/Code/pcb/work/asp-coord6.2'
--

 $ history | tail -8
  2002  git clone git://wpsoftware.net/pcb-andrew.git
  2003  cd pcb-andrew/
  2004  git checkout coord6
  2005  lsc
  2006  ./autogen.sh 
  2007  grep ./configure ~/.hist/*
  2008  ./configure --with-gui=lesstif --disable-dbus
  2009  make

Tidbit: The history command takes a numeric argument that indicates the
number of history entries to output.  You can do simply “history 8”.

Regards,
Colin


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Re: gEDA-user: Option to not display polygons

2011-08-09 Thread Colin D Bennett
On Tue, 9 Aug 2011 08:33:50 -0700
John Doty j...@noqsi.com wrote:

 You'll note that this message never appeared on the list. I never
 received the promised notification of the moderator's decision,
 either. Eyes shut tight to unwelcome truth...

Maybe it was accidentally overlooked.  The mailing list software
probably makes it easy to lose a few messages in the noise.

Regards,
Colin

 Begin forwarded message:
 
  From: John Doty j...@noqsi.com
  Date: August 2, 2011 12:56:22 PM MST
  To: Colin D Bennett co...@gibibit.com
  Cc: gEDA user mailing list geda-user@moria.seul.org, Kai-Martin
  Knaak k...@familieknaak.de Subject: Re: gEDA-user: Option to not
  display polygons
  
  
  On Aug 2, 2011, at 11:57 AM, Colin D Bennett wrote:
  
  I understand the desire to prevent spam to the list, but regular
  participants in the gEDA community shouldn't be punished
  unnecessarily.  Especially when they are contributing so much!  In
  this case, you scrambled to implement my request for a feature,
  finishing it in only a few hours!  Then it
  waited--unnecessarily--for nearly two days before it could be
  shared with the world.
  
  The problem isn't spam. The problem is that the core developers
  don't want to face certain critical issues, and define any attempt
  to bring up said issues as disrespectful, and therefore
  unprofessional. Kai-Martin is one person who is considered
  disrespectful in this sense.
  
  I personally consider this shoot the messenger attitude as
  antithesis of professionalism. It's unfortunately common in my
  business, where it causes mission failures and sometimes kills
  people.
  
  John Doty  Noqsi Aerospace, Ltd.
  http://www.noqsi.com/
  j...@noqsi.com
  
  
 
 John Doty  Noqsi Aerospace, Ltd.
 http://www.noqsi.com/
 j...@noqsi.com


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Re: gEDA-user: Option to not display polygons

2011-08-09 Thread Colin D Bennett
John and Kai-Martin,

Of course my response was intentionally, exaggeratedly generous to the
moderators... I was just trying to get something from this discussion
onto the list for public visibility.

Obviously the list moderation is not being handled in a way that
optimally supports the openness and freedom that is fundamental to the
Free Software community and the gEDA project in particular.

It would be a shame to see a mailing list fork (which I see coming)
which would split the community.

Regards,
Colin
- Happy with gEDA software... it's great
- Happy with the many great people in the gEDA community
- Not happy with moderation of geda-user mailing list


On Tue, 9 Aug 2011 09:13:54 -0700
Colin D Bennett co...@gibibit.com wrote:

 On Tue, 9 Aug 2011 08:33:50 -0700
 John Doty j...@noqsi.com wrote:
 
  You'll note that this message never appeared on the list. I never
  received the promised notification of the moderator's decision,
  either. Eyes shut tight to unwelcome truth...
 
 Maybe it was accidentally overlooked.  The mailing list software
 probably makes it easy to lose a few messages in the noise.
 
 Regards,
 Colin
 
  Begin forwarded message:
  
   From: John Doty j...@noqsi.com
   Date: August 2, 2011 12:56:22 PM MST
   To: Colin D Bennett co...@gibibit.com
   Cc: gEDA user mailing list geda-user@moria.seul.org, Kai-Martin
   Knaak k...@familieknaak.de Subject: Re: gEDA-user: Option to not
   display polygons
   
   
   On Aug 2, 2011, at 11:57 AM, Colin D Bennett wrote:
   
   I understand the desire to prevent spam to the list, but regular
   participants in the gEDA community shouldn't be punished
   unnecessarily.  Especially when they are contributing so much!
   In this case, you scrambled to implement my request for a
   feature, finishing it in only a few hours!  Then it
   waited--unnecessarily--for nearly two days before it could be
   shared with the world.
   
   The problem isn't spam. The problem is that the core developers
   don't want to face certain critical issues, and define any attempt
   to bring up said issues as disrespectful, and therefore
   unprofessional. Kai-Martin is one person who is considered
   disrespectful in this sense.
   
   I personally consider this shoot the messenger attitude as
   antithesis of professionalism. It's unfortunately common in my
   business, where it causes mission failures and sometimes kills
   people.
   
   John Doty  Noqsi Aerospace, Ltd.
   http://www.noqsi.com/
   j...@noqsi.com
   
   
  
  John Doty  Noqsi Aerospace, Ltd.
  http://www.noqsi.com/
  j...@noqsi.com
 
 
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Re: gEDA-user: Constraint-based PCB footprint design

2011-08-08 Thread Colin D Bennett
On Mon, 08 Aug 2011 03:47:25 +0100
Rob Spanton rspan...@zepler.net wrote:

 I've recently been playing around with designing footprints by
 describing a set of constraints that position features relative to
 each other.  This is rather than specifying the absolute co-ordinates
 of every feature.

Rob,

Thanks for this tool!  It is exactly what I have dreamed of, as I labor
with pencil, paper, and calculator to derive the absolute coordinates
from package and footprint drawings.

I hope you continue to develop this tool; it will be a great addition
to the gEDA pcb tool, and I would love to see more reasons to choose
gEDA over competing proprietary tools like Eagle.  (Not that I need to
be convinced... but to bring more new users to gEDA.)

Regards,
Colin


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Re: gEDA-user: Layer selective DRC

2011-08-05 Thread Colin D Bennett
On Fri, 05 Aug 2011 04:32:58 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Kai-Martin Knaak wrote:
 The correct syntax is:
   Attribute(PCB::skip-drc 1)
...
 By the way, what is the reason for the funny attribute name 
 with two colons in the middle? The source treats it just like 
 a plain string.

Organization using namespaces?  I think that is the intention for use
of the Attribute() token.

E.g., DJ has suggested for the “new grids” to use 

Attribute(grid:... value)

to allow storing the grid configuration in the .pcb layout file without
breaking backward compatibility.

Regards,
Colin


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Re: gEDA-user: Layer selective DRC

2011-08-04 Thread Colin D Bennett
On Thu, 04 Aug 2011 01:48:09 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Colin D Bennett wrote:
 
  A feature I have heard previously requested is to be able to mark
  certain layers as “no-DRC”.  For instance, to allow special trace
  elements such as antennas that the DRC thinks are incorrect shorts
  between two nets.
 
 These should be omited from update_rats, rather than be ignored on
 DRC. The DRC as it is currently implemented, does not check for
 correct connectivty. It does not detect a short.

Oh, that's right.  I forgot since I tend to consider the Optimize Rats
action and its feedback as a first pass of DRC, and the actual DRC
action as a more detailed pass... but it seems like it would be ideal
for a short to be detected by DRC.

 I think, this
 functionality would be best implemented with a flag
 don-t-check-connectivity added to the object. Put these antennas in
 a separate layer and make DRC special for this layer would still feel
 like a crutch.  

My current workaround is to actually connect the antenna input
directly to ground on the schematic, so that pcb does not complain that
the PCB trace antenna is a short.  (See attached figure from the
schematic.)  For this specific and simple purpose, this works well
enough for the moment.

Regards,
Colin
attachment: 2011-08-03_geda_antenna_drc_kludge.png

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Re: gEDA-user: .pdf to .pcb / exact coordinates

2011-08-04 Thread Colin D Bennett
On Thu, 4 Aug 2011 11:20:50 +0200 (CEST)
SZABO Tamas sza2k...@freemail.hu wrote:

 Is the any easier and accurate way to place connectors to the right
 position?
 
 Furthermore, a part of my converted pcb always outside of the pcb
 editing area. Can I center it somehow? The commands I use:
 - (print as .ps in qcad)
 - ps2epsi board.ps board.epsi
 - pstoedit -usebbfrominput board.epsi -f pcb board.pcb
 Checking board.epsi with gv, it seems correct.

You can use Inkscape to open the Postscript .ps file and then
manipulate the drawing to center it, expand the canvas, etc.
Finally you would export from Inkscape to a .eps file and continue with
pstoedit to export to pcb.

Regards,
Colin


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Re: gEDA-user: Linux Desktop für gEDA

2011-08-04 Thread Colin D Bennett
On Thu, 4 Aug 2011 21:29:39 +0300
Павел Таранов taranov.pa...@gmail.com wrote:

 I'm currently using Ubuntu 11.04 with classic Gnome (you can switch
 on GDM prompt).
 
 But Ubuntu team promice to remove this feature on next realeses...

I promise if that happens, I will to switch to Debian... and from what I
have heard I will be joined by MANY others.

 2011/8/4 Markus g...@traidl.de
 
Hello,
 
currently I am running the actual Ubunut Version and the new Unity
(Gnome 3.0) Desktop. But I am not very happy with the new desktop.

I use Gnome also.  The Unity desktop seemed interesting at first, but
it has some serious progressive slowdown bugs that completely kill it.
I switched to the Ubuntu Classic session.

I am thinking about changing to xcfe.
 
What desktop are you using for gEDA?
 
(are the any advantages or disadvantages for KDE, Gnome or XCFE
  in relation to gEDA?)

No, really it is a matter of personal preference about appearance,
configurability, and especially what “core desktop applications” you
prefer.  When I say core desktop applications, I mean that KDE,
Gnome, XFCE, etc. have many applications such as file manager, CD/DVD
burner, web browser, e-mail client, terminal applications, archive
manager, etc. that they provide or integrate most seamlessly with.
However, you can certainly mix an match.  For instance, I use Firefox
instead of Konqueror (KDE) or Epiphany (Gnome), and Claws instead of
Kmail or Evolution.  But k3b is the most powerful CD/DVD burner, so I
use that even on Gnome.  I use GIMP even on KDE.

You can certainly switch desktop managers/window managers often: just
log out, choose a different session, and log back in.  It's not a big
deal.

Regards,
Colin


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Re: gEDA-user: Layer selective DRC

2011-08-03 Thread Colin D Bennett
On Wed, 03 Aug 2011 16:24:21 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 Hi. 
 My current project calls for big currents and and fine pitch SMD
 components, too. So I opted for four layers with 35 µm copper on
 outer and 105 µm copper on inner layers. Now, my fab requests 250 µm
 clearace on layers with extra copper. To comply with this, it would
 be handy to have different sets of design rules fpor differnt layers. 
 
 In the absence of that feature, is there any way to restrict a DRC
 check just to one specific layer?

A feature I have heard previously requested is to be able to mark
certain layers as “no-DRC”.  For instance, to allow special trace
elements such as antennas that the DRC thinks are incorrect shorts
between two nets. I also would like this so that the “outline” layer or
extra layers with my own notes, calculations, fab notes, etc., are not
considered for DRC.

Regards,
Colin


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Re: gEDA-user: Wireless comms options

2011-08-02 Thread Colin D Bennett
On Tue, 02 Aug 2011 12:57:28 -0500
John Griessen j...@ecosensory.com wrote:

 On 08/02/11 03:44, Chris Smith wrote:
  I'm developing
  an application that needs to send a stream of data from one device
  to another, but I don't have much experience with wireless
 
 Not so sure about the data rate...  what does the above
 translate to in serial data bits per second?  800x600x24  all x 30fps?
 
 that's 345 Mega bits/sec!  Can you compress it and then expand at
 other end with your hardware?

He said H.264 which is significantly compressed, or composite video,
which would probably be an analog signal.

For H.264, you could possibly use 802.11g.  The possibilities really
depend on other system constraints.  What are the sending and receiving
devices?  FPGA?  DSP?  Computer with Linux?  Embedded Linux?

Regards,
Colin


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Re: gEDA-user: Option to not display polygons

2011-08-01 Thread Colin D Bennett
On Sat, 30 Jul 2011 00:44:23 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Colin D Bennett wrote:
 
  I wish it was possible to toggle visibility of individual layers
  within a group. 
 
 Your wish is my command!  :-)
 
 See the attached patch. With this patch you can use the control key
 to only toggle the visibility of the layer given by the clicked layer
 button. 

Thanks, Kai-Martin!  That is great.  Only, I don't the functionality
is quite hooked up to the Control-click yet... it still seems to toggle
the entire group when I tried it.

Regards,
Colin


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Re: gEDA-user: Problem With SOT23-5? Invisible Guardband Around Landpattern; Arcs in Silkscreen

2011-08-01 Thread Colin D Bennett
On Sun, 31 Jul 2011 23:32:46 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 DJ Delorie wrote:
 
  You can't. Footprints are strictly made from lines and rectangles.
  No arcs, no text, no weird polygons.
  
  Wrong.  The silkscreen is made from lines and arcs, no rectangles or
  polygons.
 
 I stand corrected (and should have known better, since many of my 
 footprints contain circles). For some reason, the restrictions for 
 copper in footprints floated in my mind.

How I long for full and uniform support for all drawing elements in
footprints, both copper and silk!

Regards,
Colin


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Re: gEDA-user: Option to not display polygons

2011-07-29 Thread Colin D Bennett
On Fri, 29 Jul 2011 01:58:12 +0200
Kai-Martin Knaak k...@familieknaak.de wrote:

 Hi.
 
 Just finished my latest, a bit larger layout (The one I bragged about
 lately). After I added polygons to pour the remaining board estate
 with copper, PCB slowed down significantly. Frames per second as
 measured with the benchmark() action went down from very usable 16
 FPS (*) to 1 FPS. Teh thin_draw_poly option from the setttings menu
 improved visibility but did nothing to the speed. This is no
 surprise, since it draws the same objects but with very transparent
 color.
 
 To get the GUI workable, I had to fall back to the old layer-hack:
 Move the polygons to separate layers and make them a layer group of
 their own. With this set-up the polygon layers can be selectively
 switched off and the GUI becomes snappy again. Since this is a four
 copper layers, I ended up with eight regular PCB layers. 

I wish it was possible to toggle visibility of individual layers within
a group.  Then you could leave the polygons on their own virtual
layer.  This would be useful for many other purposes as well as for
your hack.

Regards,
Colin


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Re: gEDA-user: zero-clearance pads for milled/high-power boards

2011-07-29 Thread Colin D Bennett
On Thu, 28 Jul 2011 23:39:04 -0600
jb...@frii.com wrote:

 People reading this list already know this, so this is mostly a post 
 for people who are searching the web trying to figure out how to make 
 milled or very high power/heatsinking boards in which having thermal 
 clearance around pads into copper pours is unwanted, and drawing 
 multiple overlapping traces isn't working well either.  (I figured
 this out by making a part incorrectly.)
 
 If you reduce the pad clearance to zero, a copper pour will flow
 right over it.
 The problem with this is A: it'll DRC like mad, because B: you can 
 easily short traces/pours across pads doing this.

If you use a small clearance on the pad rather than zero clearance
and then draw a short, wide LINE on the copper layer that covers the
entire pad, setting the JOIN flag on the line with
SetFlag(selected, join), then it will help avoid getting traces
shorted to the pad, at least.

Regards,
Colin


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Re: gEDA-user: Migration form eagle to gEDA

2011-07-27 Thread Colin D Bennett
On Wed, 27 Jul 2011 12:28:21 +0200
Markus Hitter m...@jump-ing.de wrote:

 Am 26.07.2011 um 07:33 schrieb bsali...@gmail.com:
 
  1. Schematic  board are decoupled so any changes to schematic need
  to be re-synced to the board. I haven't figured out the way yet.
 
 Look up and use xgsch2pcb. Everything else is too complex for  
 beginners. Emphasis on the x at the first letter.

I mentioned xgsch2pcb in my reply to this message, so I have
nothing against it.  However, I want to know how clicking
File | Import Schematics is “too complex for beginners”.

Regards,
Colin


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Re: gEDA-user: Migration form eagle to gEDA

2011-07-26 Thread Colin D Bennett
On Mon, 25 Jul 2011 22:33:11 -0700
bsali...@gmail.com bsali...@gmail.com wrote:

 Thanks for the detailed steps Colin.
 
 Sorry I was not clear I was looking to migrate as a user. Although I
 have a license for eagle but sometime get limited by the number of
 schematic sheets. So far I haven't reached max board size. I have
 moderately large customized libraries on eagle. I use git with my
 current setup as my version control mech.
 
 Couple of days back I was able to create a test schematic on gschem
 but it was not obvious to transfer the schematic to PCB. I guess it
 will take time to learn.
 
 So far I made a few observations comparing eagle:
 
 1. Schematic  board are decoupled so any changes to schematic need to
 be re-synced to the board. I haven't figured out the way yet.

There are two ways to do this: an old way, and a new way.  I can't tell
you too much about the differences since I've only really used the old
way, but the new way is simpler.

(a) The new way is to use the new File | Import Schematics command in
pcb to update the layout from the schematic.

(b) The old way is to use the gsch2pcb command line tool or the
xgsch2pcb GUI tool.

 2. Symbol and footprint libraries are decoupled for the above reasons.

Correct.  Although, the symbol and footprint libraries do need to agree
on some things like pin naming so that things are mapped correctly.
For instance, in my custom symbols and footprints, I use “P” and “N”
for my diode pin names, and “G”, “S”, and “D” for FET pins.

(In the case of FETs, I prefer to have a single schematic symbol that
is not dependent of physical pin configuration, and then a footprint
that maps the logical pins to to proper pins on the package.)

 3. A schematic element doesn't necessarily have a footprint assigned
 by default. Maybe because gschem can be used standalone (not for PCB)

This is a controversial topic among the gEDA community.  Symbols with a
footprint attribute built-in are termed “heavyweight” symbols, and
symbols that do not come with a pre-assigned footprint are called
“lightweight” symbols.  The problem with heavyweight symbols is that
there is no one-size-fits-all answer.  Are you making a through-hole
design?  Then you likely want 1/2 W through-hole resistor footprints.
Are you making an SMT design?  Then you may want 1206, 0805, 0603,
0402, or some other SMT size resistor.

It much more difficult for the case of diodes, LEDs, transistors,
capacitors, inductors, switches, etc., because of the wide range of
package options in use (even down to transistors with different B/C/E
or G/S/D pin mappings...).

You can “heavyify” certain symbols for ease of use in specific
applications, however, by taking a lightweight footprint, assigning a
footprint, and saving it in a new symbol file.

Personally, I find that I need to check and double-check every
footprint assignment in my design anyway with the actual BOM parts to
ensure there are no errors before I lay out the board.  Therefore I
prefer to have no default footprints, and force myself to assign the
proper footprint rather than getting some incorrect default that might
slip by my verification.

 I would like to know any functional (not monetary) advantages of gEDA
 over eagle, I assume that there are many.

I think the simple fact that your designs are not locked into a
proprietary system is the first advantage of gEDA.  What if EAGLE's
maker goes out of business?  Will you be able to access and edit your
designs when Windows 8 comes around if EAGLE is not ported to it?

Regards,
Colin


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Re: gEDA-user: Warp pointer nonesense

2011-07-26 Thread Colin D Bennett
On Tue, 26 Jul 2011 17:44:29 +0200
Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 Peter Clifton wrote:
 
  On a large, crammed full board, where the feature is needed the
  most, the cross hair is almost invisible in when zoomed out.
  Highlighted SMD pads does not stand out on their own. They are
  just too small.  
  
  You see the great big animated circles homing in on the part?
 
 Astonishingly, I did not see the circle on the zoomed out crammed
 board. My eyes must have been already sleeping... Now, that I know,
 what to look for, it seeems so obvious.

Another method of drawing attention to a part of the display that could
be helpful is a “tunnel vision” effect:  fade most of the display,
leaving a small area non-faded around the feature of interest.  For
instance, when Ubuntu pops up a “Administrator Access Required” dialog
requesting password entry.

Regards,
Colin


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Re: gEDA-user: Migration form eagle to gEDA

2011-07-25 Thread Colin D Bennett
On Sun, 24 Jul 2011 19:17:39 -0700
bsali...@gmail.com bsali...@gmail.com wrote:

 I guess that his question might have been asked before but is there
 any howto or tutorial to migrate from Eagle to gEDA?
 I tried Google searches but no meaningful information has been found.

Do you mean migration of particular designs (schematic/layout),
importing them to gEDA?

Or do you mean migrating as a user?

I have never used Eagle, so I can't be of any specific assistance in
that regard.  However, I can say that while there are tutorial on
gschem/PCB and the general gEDA workflow, there is a need for a good,
complete tutorial for new users.

Because gEDA is designed to support a wide variety of uses and workflow
methods, I feel it is not immediately clear to new users how to
proceed.

Let me share my basic process for designing a circuit and PCB so you
can get a feel for how the tools might be used:

0.) Set up a revision control system.
Something modern like git or Bazaar is best.
Commit frequently, and write descriptive commit messages!
(I find this useful as a journal or log to come back to myself about
what I've done on the design, not to mention saving yourself from
screwups...)

1.) Draw schematic with gschem, placing symbols and drawing net
connections.
Various steps required as part of drawing the basic schematic:

- Import any special symbols not in the default library from
  gedasymbols.org
- If you can't find the symbol you need, draw custom symbol
  in gschem, save as .sym file.
- Run a schematic design rule check (DRC) with “gnetlist”;
  fix any DRC errors.

2.) Assign footprints to all components in the schematic.
You can do this in gschem or using gattrib (table view).

- Import any special footprints from gedasymbols.org
- If you can't find an appropriate footprint, create one in the
  “pcb” tool. (Takes some practice, but after a while it becomes
  straightforward.)
- Make sure the footprints you are using are correct for the
  parts you are going to use.
- Check footprints to make sure that pin assignments from
  schematic symbol to PCB footprint is correct!! Watch out for
  LEDs, diodes, polarized capacitors, etc. that may have pins
  identified only as “1” and “2”.  (I often use my own custom
  symbols/footprints with more descriptive, logical pin identifiers
  like “P” and “N” on diodes for P-type and N-type terminals.)

3.) Lay out the board.
- Import schematic into pcb.
- Set “preferences” for the design such as minimum copper
  clearance, board dimensions, layer stackup, etc.
- Set up the grid as you prefer.
- Place components.
- Route tracks with lines.  (You can use autorouter, but that is a
  personal preference... I have always done manual routing.)
- Draw board outline on the “outline” layer.
- Add ground flood if desired.

4.) Verify design.
- Run DRC in the pcb program; fix any problems such as “copper areas
  too close”, etc.
- Print out the PCB layout at 1:1 scale on paper and actually place
  the parts on it.  This is a sanity check to make sure footprints
  are correct and spacing around certain parts are sufficient
  (e.g., need enough spacing around some connectors, switches,
  jumpers, sockets, heat sinks, etc.).

I'm no wizard, just a novice, but I've done a few dozen designs and am
feeling very comfortable in gEDA myself so hopefully this is helpful.

One thing that I've found is that it is worthwhile to “error-proof”
yourself through your process.  Some of the common errors I've made are
related to incorrect pin assignments or footprint assignments, so I
take special care to validate those.

Regards,
Colin


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Re: gEDA-user: Design Nark

2011-07-19 Thread Colin D Bennett
On Tue, 19 Jul 2011 13:01:13 +0100
Andy Fierman andyfier...@signality.co.uk wrote:

 Is it just me being a Grumpy Old Man or does anyone else take issue
 with RS over their advertising for their Design Spark EDA tool?

Everyone should demand truth in advertising!  ...Grumpy Old Men and
Irreverent Young Kids alike.

 In particular the statement at the end of the last paragraph in:
 
 http://www.designspark.com/content/designspark-pcb-version-2-takes-pcb-design-another-dimension
 
 that With the release of DesignSpark PCB Version 2, RS has reaffirmed
 its commitment to delivering the best open source experience to its
 engineering community.

That statement is obviously false:  DesignSpark is not open source (no
matter what understanding of “open source” one holds).

 I suppose RS do only claim to be delivering whatever it is that they
 are delivering, to its engineering community., i.e. not to anyone
 else's.

That doesn't make any sense to me.

 To a lesser extent I find the statement here:
 
 http://www.designspark.com/theme/designspark-pcb
 
 that DesignSpark PCB is the world's most powerful free of charge PCB
 design tool. a bit presumptuous too.

In advertising, everyone uses superlatives, when clearly all the
competing products cannot simultaneously be the best.  An objective
side-by-side comparison of alternatives is always useful.

What is RS's criteria for “most powerful” PCB design tool?  Personally,
I am scared of having my designs locked down by a proprietary tool.
What if DesignSpark is discontinued next year or RS decides to start
charging $$$ for it?  Will I be able to still access, edit, and
manipulate my designs ten years from now, when all computers are
128-bit 64-core ARMv24 machines running Linux 3.0 and the new
Windows 2022 is available only as a pay-by-the-hour cloud computing
service with built-in pop-up ads?
... Maybe an extreme example, but really: what if DesignSpark was
discontinued next year, and didn't support Windows 8?

The openness and simplicity of the gEDA file formats and the free and
open nature of the software itself, not to mention decent (?) platform
independence, make it a stellar choice for future-proofing your designs.

Regards,
Colin


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Re: gEDA-user: Design Nark

2011-07-19 Thread Colin D Bennett
On Tue, 19 Jul 2011 11:38:25 -0700
Steven Michalske smichal...@gmail.com wrote:

 Agreed, but to remove them we need to make the script that replaces
 current functionality.
 It would be nice to see the hierarchy expander open up the pins to
 gschem file for a large connector, on say an auto symbol.  Where
 auto symbol means a symbol that is defined by a script not by a
 static file.

And not m4 script, please!  Ideally various scripting languages could
be used (Python, Perl, Scheme, Lua, etc.) as various users prefer.
Personally, I would be happy with a clean language such as either
Python or Lua.

Regards,
Colin


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Re: gEDA-user: Design Nark

2011-07-19 Thread Colin D Bennett
On Tue, 19 Jul 2011 16:56:18 -0300
Adrian Pardini pardo.b...@gmail.com wrote:

 On 19/07/2011, Colin D Bennett co...@gibibit.com wrote:
 
  And not m4 script, please!  Ideally various scripting languages
  could be used (Python, Perl, Scheme, Lua, etc.) as various users
  prefer. Personally, I would be happy with a clean language such as
  either Python or Lua.
 
 
 How about a symbol with an 'execute' attribute, when it is found it
 runs whatever is there passing the rest of the attributes as
 parameters or via stdin, then outputting the result. Even something
 like shar could be implemented, so the script and the symbol are in
 one file. Of course this opens the problem of checking third party
 symbols from nasty stuff inside.

That's a nice general-purpose idea.  But as you mention, it is a
serious security hole that we can avoid with some more supporting
code.  For instance, a sandboxed Lua environment is trivial to
implement.

 Maybe I looked into wrong places but something to filter the current
 selection / buffer with an external program would be useful too.

That would be useful, too.

Regards,
Colin


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Re: gEDA-user: pcb grid improvements... status of patch?

2011-07-13 Thread Colin D Bennett
On Wed, 13 Jul 2011 19:55:02 +0200
Gabriel Paubert paub...@iram.es wrote:

 On Wed, Jul 13, 2011 at 08:30:43PM -0700, Andrew Poelstra wrote:
  These too will be changed as we move away from a strict mm/mil
  configuration.
  
  I'm not sure what to do about them. Right now I have a giant
  table of default/max/min for all these units, which totals 12
  values per unit. Times ten currently-supported units, this is
  120 values!
  
  Storing defaults for all of them would require 40 lines...
  including things like cm, km, cmil, that most users would
  never use. Then what happens when we add support for new
  units? For user-defined units?
 
 Great. As an astronomer, I really need to be able to define
 my PCB in astronomical units and parsecs :-) 

You'll have to wait for 64-bit internal unit storage...
(when metric internals [nm units] is implemented)

Regards,
Colin


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Re: gEDA-user: pcb grid improvements... status of patch?

2011-07-13 Thread Colin D Bennett
On Wed, 13 Jul 2011 20:30:43 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Wed, Jul 13, 2011 at 02:09:13AM +0200, Kai-Martin Knaak wrote:
  There is already some information in user preference that should 
  really be configurabel on a per project base. Skipping through the
  file:
  
  grid-units-mm = 1
 
 This will turn into
   grid-units = mm
 
 I was quite frustrated to find that the .pcb file format has no
 way to store this (though it does store the grid visibility).
 Right now we check the grid spacing and try to guess which of
 mm/mil the user was using.
 
 Likely I will use an (Attribute grid-unit mm) for this in
 future.

DJ suggests using a hierarchical namespacing of the Attribute names, as
in 

  Attribute(grid:unit mm);

Such organization of the Attribute namespace would help greatly.

Regards,
Colin


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Re: gEDA-user: pcb grid improvements... status of patch?

2011-07-13 Thread Colin D Bennett
On Wed, 13 Jul 2011 11:05:56 -0700
Colin D Bennett co...@gibibit.com wrote:

 On Wed, 13 Jul 2011 19:55:02 +0200
 Gabriel Paubert paub...@iram.es wrote:
 
  Great. As an astronomer, I really need to be able to define
  my PCB in astronomical units and parsecs :-) 
 
 You'll have to wait for 64-bit internal unit storage...
 (when metric internals [nm units] is implemented)

Correcting myself:
2**64 nm ≈ 0.123 AU
2**128 nm ≈ (2.3×10**18) AU

I guess 64-bit numbers won't do it for you!

Regards,
Colin


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Re: gEDA-user: pcb GL can't render stretched arcs

2011-07-13 Thread Colin D Bennett
On Wed, 13 Jul 2011 10:02:28 -0600
Mark Rages markra...@gmail.com wrote:

 Stretched arcs are a misfeature.  Can they be deprecated?
 
 Otherwise, they are just another object that cannot be rotated at
 arbitrary angles.

There is no inherent reason elliptical arcs cannot be rotated
arbitrarily.  Any restriction on such rotation is simply due to
implementation faults in pcb.

Regards,
Colin


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Re: gEDA-user: Gtk grid changes on mm/mil toggle

2011-07-12 Thread Colin D Bennett
On Tue, 12 Jul 2011 04:46:11 -0700
Andrew Poelstra as...@sfu.ca wrote:

 
 Hey all,
 
 
 Right now in the Gtk HID when you change grid units between
 mm/mil, it will try to translate your grid setting into the
 new units by finding something sufficiently close in the
 menu.
...
 To the user, this would appear to be a randomly-selected,
 unannounced, unintended, subtle setting change.
 
 Can I remove this behavior?

Please do so!!!

While I really would like the advanced user-defined grids as in the
recent patch, at least fixing this will help.  Often I want to measure
something in mils as I am laying out components on a metric grid.  So I
click the mm/mil toggle and forget that it also switches the grid (very
subtly since it picks a mil grid close to the metric grid!).  Then I
end up continuing my layout work on the wrong grid!

I would prefer the snap grid to be independent of the display units, or
make this configurable.

Regards,
Colin


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gEDA-user: pcb grid improvements... status of patch?

2011-07-12 Thread Colin D Bennett
On Tue, 12 Jul 2011 09:52:38 -0700
Colin D Bennett co...@gibibit.com wrote:

 While I really would like the advanced user-defined grids as in the
 recent patch, at least fixing this will help.  Often I want to measure
 something in mils as I am laying out components on a metric grid.  So
 I click the mm/mil toggle and forget that it also switches the grid
 (very subtly since it picks a mil grid close to the metric grid!).
 Then I end up continuing my layout work on the wrong grid!

To follow up on this, the bug with the new patch is at
https://bugs.launchpad.net/pcb/+bug/724154
also see the geda-user mailing list thread titled “Please test new
grids for GTK PCB” started 24 Feb 2011:
http://thread.gmane.org/gmane.comp.cad.geda.user/35867/

I hope this patch can be finished and landed soon!

Regards,
Colin


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Re: gEDA-user: gschem command line printing

2011-07-12 Thread Colin D Bennett
On Tue, 12 Jul 2011 14:05:22 +0200
Michael Theurl michael.the...@smog.at wrote:

 Hello Chris,
 
 That's sounds great. 
 Maybe i can help you, i wrote a script to export pdfs and handbooks
 for geda/pcb projects. I Attach you the script. I use Fedora Core 14
 with the standart geda-gaf rpms.
 
 And it works perfectly.
 
 you need ghostscript  a project file and the createPCB.sh script
 
 example project:
 -
 schematics schem1.sch schem2.sch
 output-name masterboard
 elements-dir ~/gaf/pcb-elements/using
 -
 
 change the path in the createPCB.sh for the print.scm to your needs.

Thanks for posting your createPCB.sh script.  I have a question,
though: why do you use pcb -x bom to create the BOM instead of using
gnetlist on the .sch file?  The gnetlist option allows much more detail
in the BOM since you can use the 'attribs' file to customize the data
and include fields such as “manufacturer_partnum”, “comment”, etc.
Is there some benefit to using pcb for the BOM that I am missing?

Regards,
Colin


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Re: gEDA-user: pcb grid improvements... status of patch?

2011-07-12 Thread Colin D Bennett
On Tue, 12 Jul 2011 21:06:02 -0700
Andrew Poelstra as...@sfu.ca wrote:

 On Tue, Jul 12, 2011 at 10:48:38AM -0700, Colin D Bennett wrote:
  
  To follow up on this, the bug with the new patch is at
  https://bugs.launchpad.net/pcb/+bug/724154
  also see the geda-user mailing list thread titled “Please test new
  grids for GTK PCB” started 24 Feb 2011:
  http://thread.gmane.org/gmane.comp.cad.geda.user/35867/
 
 
 I have read through that bug report, though I haven't had
 a change to apply and play with the attached patch. The
 holdup right now is the file format change. We can't have
 that.
 
 Maybe we can store the grids in user preferences instead,
 but that's potentially a fair bit of work.

As I suggested in the bug comments, we should be able to use
“attributes” in the .pcb file without causing compatibility problems.

Regards,
Colin


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Re: gEDA-user: pcb grid improvements... status of patch?

2011-07-12 Thread Colin D Bennett
On Tue, 12 Jul 2011 21:06:02 -0700
Andrew Poelstra as...@sfu.ca wrote:

 Maybe we can store the grids in user preferences instead,
 but that's potentially a fair bit of work.

Regardless of implementation difficulty, user preferences are NOT the
place to store grid configurations, since each layout will surely have
its own grid setup depending on the component packages and physical
constraints (board density etc.).

Regards,
Colin


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