[gem5-users] X86 full system with mutlicore
Dear M5, I'm now trying to simulate a full system with more than 1 core (CPU). With image x86_64-vmlinux-2.6.22.9, I got following messages in m5term: markcup:~/Gem5/m5_new$ ./build/X86_FS/m5.debug configs/example/fs.py -n 4 m5 slave terminal: Terminal 0 Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007 Command line: earlyprintk=ttyS0 console=ttyS0 lpj=723 root=/dev/hda1 BIOS-provided physical RAM map: BIOS-e820: - 0010 (reserved) BIOS-e820: 0010 - 0800 (usable) end_pfn_map = 32768 kernel direct mapping tables up to 800 @ 10-102000 DMI 2.5 present. Zone PFN ranges: DMA 256 - 4096 DMA324096 - 1048576 Normal1048576 - 1048576 early_node_map[1] active PFN ranges 0: 256 -32768 Intel MultiProcessor Specification v1.4 MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE0 Processor #0 (Bootup-CPU) Processor #1 WARNING: NR_CPUS limit of 1 reached. Processor ignored. Processor #2 WARNING: NR_CPUS limit of 1 reached. Processor ignored. Processor #3 WARNING: NR_CPUS limit of 1 reached. Processor ignored. I/O APIC #4 at 0xFEC0. Setting APIC routing to flat Processors: 1 .. Then, I follow the page http://www.m5sim.org/wiki/index.php/Compiling_a_Linux_Kernel, and make linux-2.6.28 image with config file for 2.6.28.4 (from http://www.m5sim.org/Download), but it's still not working. Dose X86 have Linux patches and modified PAL code which are like Alpha_FS? (http://www.m5sim.org/Frequently_Asked_Questions#How_many_CPUs_can_M5_run.3F) Thank you. Mark Chen ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 full system with mutlicore
X86 doesn't have PAL code so you don't have to worry about that. There are Linux patches for it, but those aren't necessary for it to work properly, they just help the simulator run faster. There's a configuration option for the kernel that sets how many CPUs it supports. That's probably set to 1. Gabe On 06/03/11 05:44, 冠男陳 wrote: Dear M5, I'm now trying to simulate a full system with more than 1 core (CPU). With image x86_64-vmlinux-2.6.22.9, I got following messages in m5term: markcup:~/Gem5/m5_new$ ./build/X86_FS/m5.debug configs/example/fs.py -n 4 m5 slave terminal: Terminal 0 Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007 Command line: earlyprintk=ttyS0 console=ttyS0 lpj=723 root=/dev/hda1 BIOS-provided physical RAM map: BIOS-e820: - 0010 (reserved) BIOS-e820: 0010 - 0800 (usable) end_pfn_map = 32768 kernel direct mapping tables up to 800 @ 10-102000 DMI 2.5 present. Zone PFN ranges: DMA 256 - 4096 DMA324096 - 1048576 Normal1048576 - 1048576 early_node_map[1] active PFN ranges 0: 256 -32768 Intel MultiProcessor Specification v1.4 MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE0 Processor #0 (Bootup-CPU) Processor #1 WARNING: NR_CPUS limit of 1 reached. Processor ignored. Processor #2 WARNING: NR_CPUS limit of 1 reached. Processor ignored. Processor #3 WARNING: NR_CPUS limit of 1 reached. Processor ignored. I/O APIC #4 at 0xFEC0. Setting APIC routing to flat Processors: 1 .. Then, I follow the page http://www.m5sim.org/wiki/index.php/Compiling_a_Linux_Kernel, and make linux-2.6.28 image with config file for 2.6.28.4 (from http://www.m5sim.org/Download), but it's still not working. Dose X86 have Linux patches and modified PAL code which are like Alpha_FS? (http://www.m5sim.org/Frequently_Asked_Questions#How_many_CPUs_can_M5_run.3F) Thank you. Mark Chen ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Question about checkpoint
Hi Atieh, This is a tricky question to answer, because it depends on a lot of other configuration parameters. If you are using the ALPHA or x86 architectures, I know that checkpointing works for both SE and FS. The other architectures might also work, but I'd have to defer to others on the list about what parts of the checkpointing functionality works for each ISA. If you're using the classic memory model in gem5 (the default), it's worth noting that cache state is not checkpointed, so when you restore, the caches are cold. On the other hand, the Ruby memory model has functionality to checkpoint the caches. Hope this helps, Joel On Thu, Jun 2, 2011 at 12:55 AM, Atieh Lotfi ati.lo...@gmail.com wrote: Hi Joel, Thank you so much for your help. It would be kind of you if you would let me know, is it possible to restore from checkpoints in SE mode?or it just works in FS mode? Regards, Atieh On Wed, Jun 1, 2011 at 8:41 PM, Joel Hestness hestn...@cs.utexas.eduwrote: Hi Atieh, You can take checkpoints within the benchmark by instrumenting the code with the M5 magic instructions. You will need to grab a few files from ./util/m5/ and move them to the source tree of your benchmark: m5op.h, m5ops.h and m5op_arch.S (where arch is the ISA that you're building the benchmark for). You will need to include the m5op.h header in the source code that you're instrumenting, and you will need to build and link against the m5op_arch.S assembly file. As an example of how the instrumentation works, you can check out the m5 control application, ./util/m5/m5.c, and the appropriate Makefiles in ./util/m5. Hope this helps, Joel On Tue, May 31, 2011 at 5:30 AM, Atieh Lotfi ati.lo...@gmail.com wrote: Hi, I have some questions about checkpoitning mechanism in gem5. Is it possible to control the checkpoint from the benchmark itself and not to control it from the command line? I don’t want to take periodic checkpoints. I want to determine some points in the benchmark for taking checkpoints. I also have another question. I want to know over and above serialize.c, which c codes are related to getting checkpoints? Thanks in advance, Regards, Atieh ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] InOrder ALPHA SE. Confusion about implementation of the ActivityRecorder
Hi All, I am working with the InOrder CPU model for ALPHA ISA in SE mode. I have attached a monitoring unit, parallel to the main InOrder CPU pipeline. This monitoring unit is itself pipelined and am making use of the another instantiation of the TimeBufferStruct to communicate between its stages. I notice that in the code, some activity monitoring happens with respect to the main instruction pipeline stages and the CPU is put to sleep when no activity is recorded in the any stage of the pipeline. I want this activity recorder to keep into account the activity in my monitoring unit as well, so that if some processing is going on there, the CPU is not put to sleep. Can somebody help me out in this. I checked the files activityRec.c, but I don't understand it properly. Also, I notice that in the cpu files, the activity recorder is instantiated as:- activityRec(params-name, NumStages, 10, params-activity) = Why is the longest latency 10 here, if numStages = 5?Is there some correlation? Is there some documentation which speaks about it. To also monitor the activity in the separate monitoring unit, should I make changes to the same activityRec structure, as in increase the numstages to the total number of instruction pipeline stages + number of stages in the monitoring unit? Can somebody help me out with this? Thanks, Reena ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
